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Added help messages to ilang and verilog frontends

This commit is contained in:
Clifford Wolf 2013-03-01 08:03:00 +01:00
parent 51c2b797b3
commit 8a6b0a3520
3 changed files with 60 additions and 2 deletions

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README
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@ -170,6 +170,9 @@ Verilog Attributes and non-standard features
- The 'full_case' attribute on case statements is supported
(also the non-standard "// synopsys full_case" directive)
- The 'parallel_case' attribute on case statements is supported
(also the non-standard "// synopsys parallel_case" directive)
- The "// synopsys translate_off" and "// synopsys translate_on"
directives are also supported (but the use of `ifdef .. `endif
is strongly recommended instead).