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Added constant size expression support of sized constants

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Clifford Wolf 2014-02-01 13:50:23 +01:00
parent 1e2440e7ed
commit d06258f74f
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@ -275,6 +275,10 @@ Verilog Attributes and non-standard features
always block: "assert(<expression>);". It is transformed to a $assert cell
that is supported by the "sat" and "write_btor" commands.
- Sized constants (the syntax <size>'s?[bodh]<value>) support constant
expressions as <size>. If the expresion is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
Workarounds for known build problems
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