nella
fc71719e6e
Rename csa_tree to arith_tree.
2026-04-13 12:48:05 +02:00
nella
c3c577f333
Fix test cases.
2026-04-13 12:48:05 +02:00
nella
42c309347b
Clarify.
2026-04-13 12:48:05 +02:00
nella
4f4c820f73
Cleaned up CSA tests.
2026-04-13 12:48:05 +02:00
nella
9cc2e7d95e
rm misc comments.
2026-04-13 12:48:05 +02:00
nella
9dc408eea7
CSA add alumacc related tests.
2026-04-13 12:48:05 +02:00
nella
fc9adae9a2
Consolidate csa tests.
2026-04-13 12:48:05 +02:00
nella
ab1c423692
Tighten csa tests.
2026-04-13 12:48:05 +02:00
nella
cfee6bb4af
Add more robsutness tests.
2026-04-13 12:48:05 +02:00
nella
6b0caedcdd
Add chain tests and tighten synthesis assertions for csa.
2026-04-13 12:48:05 +02:00
nella
7183016910
Edge case tests.
2026-04-13 12:48:05 +02:00
nella
1a4a41812c
Add csa synth tests.
2026-04-13 12:48:05 +02:00
nella
4c4c5cf15a
Add structural tests for csa_tree.
2026-04-13 12:48:05 +02:00
Emil J
86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef
...
Undefine set&reset behavior of $dffsr
2026-04-08 14:22:34 +00:00
Emil J
cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port
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muxpack: fix wide Y port handling
2026-03-31 10:49:39 +00:00
Gus Smith
6a5fea1b27
Regression test for #5765
2026-03-30 08:59:28 -07:00
Miodrag Milanovic
417e871b06
Fix tests due to ABC improvements
2026-03-30 15:23:27 +01:00
Miodrag Milanović
cc915b4c76
Merge pull request #5717 from zaun/latch-support
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gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
2026-03-23 16:51:30 +00:00
Emil J
7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init
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genrtlil: fast memory initialization
2026-03-23 10:21:21 +00:00
Emil J. Tywoniak
12b443e71c
dfflibmap: consistent clk2fflogic usage in test
2026-03-19 19:48:25 +01:00
Emil J
9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection
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setundef: respect selection for cells, processes, and connections
2026-03-18 22:53:06 +00:00
Emil J. Tywoniak
27737c6e2e
rtlil: add remove2 unit test
2026-03-18 23:33:35 +01:00
Lofty
c4cc53a72e
synth: fix after abc -fast removal
2026-03-18 17:59:58 +01:00
Emil J
c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean
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Parallelize `opt_clean` pass
2026-03-16 09:52:34 +00:00
abhinavputhran
314d01b35f
changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change
2026-03-08 20:14:03 -04:00
abhinavputhran
47c2257f82
setundef: more tests! and wire selection in -init mode
2026-03-08 19:41:31 -04:00
abhinavputhran
c23ba3f917
I think CI runs within the tests directory based on error so I changed the file path
2026-03-08 18:15:35 -04:00
abhinavputhran
5048dac854
setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer
2026-03-06 18:12:03 -05:00
Lofty
050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices
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synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
2026-03-06 08:57:59 +00:00
Miodrag Milanovic
602f3fd1a5
Add missing EOL
2026-03-06 09:10:55 +01:00
Miodrag Milanovic
52533b0d1c
Update opt_lut_ins and stat for analogdevices and remove ecp5
2026-03-06 09:10:36 +01:00
Robert O'Callahan
1260fda83a
Add 'init' attributes to RTLIL fuzzing
2026-03-06 02:20:08 +00:00
Robert O'Callahan
cdfc586f18
Add unit tests for ConcurrentWorkQueue
2026-03-06 02:20:08 +00:00
Robert O'Callahan
1e96328ede
Add some tests for ShardedHashSet
2026-03-06 02:20:08 +00:00
Robert O'Callahan
3910d569da
Add unit tests for ConcurrentQueue and ThreadPool
2026-03-06 02:20:08 +00:00
Robert O'Callahan
ac55935a68
Add unit-tests for ParallelDispatchThread and friends
2026-03-06 02:20:08 +00:00
Robert O'Callahan
7f3b11e56b
Add test that connects a wire with init to a constant
2026-03-06 02:20:08 +00:00
Justin Zaun
9288889e20
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
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Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
2026-03-05 16:04:23 +01:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment
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ast: Add support for array-to-array assignment
2026-03-05 11:10:12 +00:00
Lofty
cd60dd4912
synth_analogdevices: update timing model and tests
2026-03-05 05:37:13 +00:00
Krystine Sherwin
5d3ed5a418
analogdevices: Extra tests
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`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2026-03-05 05:37:13 +00:00
Lofty
39cb61615f
analogdevices: DSP inference
2026-03-05 05:37:12 +00:00
Krystine Sherwin
9be3cfb3f9
analogdevices: Update lutram.ys test
2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5
test suite
2026-03-05 05:37:12 +00:00
Andrew Pullin
6ac8c8cb05
ast: Add support for array-to-array assignment
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This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:
1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`
Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.
Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
2026-03-04 21:34:40 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
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celltypes: compile-time lookup tables for internal cells
2026-03-04 14:47:57 +00:00
nella
b8ee0803ab
Remove todo.
2026-03-04 12:39:45 +01:00
nella
66bd4716cf
rtlil use newcelltypes.
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
6d4736269b
newcelltypes: extend testing
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ae10e9e955
pyosys: disable test
2026-03-04 12:39:45 +01:00
