mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-03-19 11:33:11 +00:00
Code Activity

setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer

Browse source
This commit is contained in:
abhinavputhran 2026-03-06 18:12:03 -05:00
parent 9e666c727f
commit 5048dac854
3 changed files with 52 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

23
passes/cmds/setundef.cc
View file

@ -330,12 +330,12 @@ struct SetundefPass : public Pass {
SigMap sigmap(module);
SigPool undriven_signals;
for (auto &it : module->wires_)
undriven_signals.add(sigmap(it.second));
for (auto wire : module->selected_wires())
undriven_signals.add(sigmap(wire));
for (auto &it : module->wires_)
if (it.second->port_input)
undriven_signals.del(sigmap(it.second));
for (auto wire : module->selected_wires())
if (wire->port_input)
undriven_signals.del(sigmap(wire));
CellTypes ct(design);
for (auto &it : module->cells_)
@ -345,8 +345,6 @@ struct SetundefPass : public Pass {
RTLIL::SigSpec sig = undriven_signals.export_all();
for (auto &c : sig.chunks()) {
if (!design->selected(module, c.wire))
continue;
RTLIL::SigSpec bits;
if (worker.next_bit_mode == MODE_ANYSEQ)
bits = module->Anyseq(NEW_ID, c.width);
@ -366,7 +364,7 @@ struct SetundefPass : public Pass {
pool<SigBit> ffbits;
pool<Wire*> initwires;
for (auto cell : module->cells())
for (auto cell : module->selected_cells())
{
if (!cell->is_builtin_ff())
continue;
@ -421,9 +419,6 @@ struct SetundefPass : public Pass {
if (wire->name[0] == (wire_types ? '\\' : '$'))
continue;
if (!design->selected(module, wire))
continue;
if (!wire->attributes.count(ID::init))
continue;
@ -453,9 +448,6 @@ struct SetundefPass : public Pass {
if (wire->name[0] == (wire_types ? '\\' : '$'))
continue;
if (!design->selected(module, wire))
continue;
for (auto bit : sigmap(wire))
if (!ffbits.count(bit))
goto next_wire;
@ -477,9 +469,6 @@ struct SetundefPass : public Pass {
if (wire->name[0] == (wire_types ? '\\' : '$'))
continue;
if (!design->selected(module, wire))
continue;
for (auto bit : sigmap(wire))
if (ffbits.count(bit))
initwires.insert(wire);

27
tests/various/setundef_selection.ys Normal file
View file

@ -0,0 +1,27 @@
# Test that setundef -zero respects wire selection: only selected wire is changed
read_verilog <<EOT
module test;
wire a = 1'bx;
wire b = 1'bx;
endmodule
EOT
setundef -zero w:a
sat -prove a 0
design -reset
# Test that setundef -undriven -zero respects wire selection
read_verilog <<EOT
module test(output wire a, output wire b);
assign a = 1'b0;
endmodule
EOT
setundef -undriven -zero w:b
sat -prove b 0
design -reset
# Test that setundef -init respects cell selection: only selected FF gets init set
read_rtlil tests/various/setundef_selection_ff.il
setundef -init -zero c:myff_a
# only wire a should have init attribute, not b
select -assert-count 1 w:* a:init %i
design -reset

19
tests/various/setundef_selection_ff.il Normal file
View file

@ -0,0 +1,19 @@
module \test
wire input 1 \clk
wire output 2 \a
wire output 3 \b
cell $dff \myff_a
parameter \WIDTH 1
parameter \CLK_POLARITY 1'1
connect \D \a
connect \Q \a
connect \CLK \clk
end
cell $dff \myff_b
parameter \WIDTH 1
parameter \CLK_POLARITY 1'1
connect \D \b
connect \Q \b
connect \CLK \clk
end
end