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gowin: add hardware latch support (DL/DLN/DLC/DLP variants)

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Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
This commit is contained in:
Justin Zaun 2026-03-01 16:11:30 -10:00 • committed by Miodrag Milanović
parent 95d738edc0
commit 9288889e20
5 changed files with 175 additions and 4 deletions
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25
tests/arch/gowin/latches.ys Normal file
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read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:DL
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DL t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top latchn
proc
equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:DLN
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:DLN t:IBUF t:OBUF %% t:* %D