changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change

tests/various/setundef_selection.ys

@@ -11,7 +11,7 @@ sat -enable_undef -prove b 0 -falsify
 design -reset
 
 # Test that setundef -undriven -zero respects wire selection
-read_rtlil setundef_selection_undriven.il
+read_verilog setundef_selection_undriven.v
 setundef -undriven -zero w:b
 sat -prove b 0
 sat -enable_undef -prove a 0 -falsify

tests/various/setundef_selection_undriven.il

@@ -1,4 +0,0 @@
-module \test
-  wire output 1 \a
-  wire output 2 \b
-end

tests/various/setundef_selection_undriven.v

@@ -0,0 +1,4 @@
+module test;
+    wire a;
+    wire b;
+endmodule