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Update opt_lut_ins and stat for analogdevices and remove ecp5
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5 changed files with 16 additions and 15 deletions
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@ -19,7 +19,7 @@ end
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EOF
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read_verilog -lib +/analogdevices/cells_sim.v
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equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech xilinx
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equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech analogdevices
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design -load postopt
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@ -23,7 +23,7 @@ EOF
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read_verilog -lib +/ecp5/cells_sim.v
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equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5
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equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech lattice
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design -load postopt
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