Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection

setundef: respect selection for cells, processes, and connections

tests/various/setundef_selection.ys

@@ -0,0 +1,32 @@
+# Test that setundef -zero respects wire selection: only selected wire is changed
+read_verilog <<EOT
+module test;
+    wire a = 1'bx;
+    wire b = 1'bx;
+endmodule
+EOT
+setundef -zero w:a
+sat -prove a 0
+sat -enable_undef -prove b 0 -falsify
+design -reset
+
+# Test that setundef -undriven -zero respects wire selection
+read_verilog setundef_selection_undriven.v
+setundef -undriven -zero w:b
+sat -prove b 0
+sat -enable_undef -prove a 0 -falsify
+design -reset
+
+# Test that setundef -init respects cell selection: only selected FF gets init set
+read_rtlil setundef_selection_ff.il
+setundef -init -zero c:myff_a
+select -assert-count 1 w:* a:init %i
+select -assert-count 0 w:b a:init %i
+design -reset
+
+# Test that setundef -init works with wire selection
+read_rtlil setundef_selection_ff.il
+setundef -init -zero w:a
+select -assert-count 1 w:* a:init %i
+select -assert-count 0 w:b a:init %i
+design -reset

tests/various/setundef_selection_ff.il

@@ -0,0 +1,19 @@
+module \test
+  wire input 1 \clk
+  wire output 2 \a
+  wire output 3 \b
+  cell $dff \myff_a
+    parameter \WIDTH 1
+    parameter \CLK_POLARITY 1'1
+    connect \D \a
+    connect \Q \a
+    connect \CLK \clk
+  end
+  cell $dff \myff_b
+    parameter \WIDTH 1
+    parameter \CLK_POLARITY 1'1
+    connect \D \b
+    connect \Q \b
+    connect \CLK \clk
+  end
+end

tests/various/setundef_selection_undriven.v

@@ -0,0 +1,4 @@
+module test;
+    wire a;
+    wire b;
+endmodule