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Merge pull request #5763 from YosysHQ/emil/c-slow-init
genrtlil: fast memory initialization
This commit is contained in:
Emil J
GitHub
commit
7b2ab9b245
3 changed files with 460 additions and 43 deletions
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@ -342,6 +342,9 @@ struct AST_INTERNAL::ProcessGenerator
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// The most recently assigned $print or $check cell \PRIORITY.
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int last_effect_priority;
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// Track which signals have been assigned in current_case to avoid unnecessary removeSignalFromCaseTree calls
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pool<RTLIL::SigBit> current_case_assigned_bits;
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ProcessGenerator(std::unique_ptr<AstNode> a, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(std::move(a)), initSyncSignals(initSyncSignalsArg), last_effect_priority(0)
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{
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// rewrite lookahead references
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@ -430,6 +433,10 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
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} else {
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addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
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// Track initial assignments
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for (auto &bit : subst_lvalue_to)
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if (bit.wire != NULL)
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current_case_assigned_bits.insert(bit);
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}
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// process the AST
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@ -557,14 +564,42 @@ struct AST_INTERNAL::ProcessGenerator
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// e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
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// function is called to clean up the first two assignments as they are overwritten by
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// the third assignment.
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void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
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void removeSignalFromCaseTree(const pool<RTLIL::SigBit> &pattern_bits, RTLIL::CaseRule *cs)
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{
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for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
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it->first.remove2(pattern, &it->second);
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// Optimization: check actions in reverse order and stop early if we've found all pattern bits
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pool<RTLIL::SigBit> remaining_bits = pattern_bits;
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for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) {
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bool has_pattern = false;
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for (auto &bit : it->first) {
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if (bit.wire != NULL && remaining_bits.count(bit)) {
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has_pattern = true;
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remaining_bits.erase(bit);
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}
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}
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if (has_pattern) {
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it->first.remove2(pattern_bits, &it->second);
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}
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// Early exit if we've processed all bits in pattern
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if (remaining_bits.empty())
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break;
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}
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for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
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for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
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removeSignalFromCaseTree(pattern, *it2);
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removeSignalFromCaseTree(pattern_bits, *it2);
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}
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void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
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{
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pool<RTLIL::SigBit> pattern_bits;
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pattern_bits.reserve(pattern.size());
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for (auto &bit : pattern)
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if (bit.wire != NULL)
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pattern_bits.insert(bit);
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removeSignalFromCaseTree(pattern_bits, cs);
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}
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// add an assignment (aka "action") but split it up in chunks. this way huge assignments
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@ -623,7 +658,23 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
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}
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removeSignalFromCaseTree(lvalue, current_case);
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// Check if any bits in lvalue have been assigned before in current_case
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bool has_overlap = false;
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for (auto &bit : lvalue) {
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if (bit.wire != NULL && current_case_assigned_bits.count(bit)) {
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has_overlap = true;
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break;
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}
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}
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if (has_overlap)
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removeSignalFromCaseTree(lvalue, current_case);
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// Track newly assigned bits
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for (auto &bit : lvalue)
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if (bit.wire != NULL)
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current_case_assigned_bits.insert(bit);
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remove_unwanted_lvalue_bits(lvalue, rvalue);
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current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
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}
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@ -670,9 +721,15 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::CaseRule *backup_case = current_case;
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current_case = new RTLIL::CaseRule;
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pool<RTLIL::SigBit> backup_assigned_bits = std::move(current_case_assigned_bits);
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current_case_assigned_bits.clear();
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set_src_attr(current_case, child.get());
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last_generated_case = current_case;
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addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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// Track temp assignments
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for (auto &bit : this_case_eq_ltemp)
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if (bit.wire != NULL)
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current_case_assigned_bits.insert(bit);
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for (auto& node : child->children) {
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if (node->type == AST_DEFAULT)
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default_case = current_case;
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@ -686,6 +743,7 @@ struct AST_INTERNAL::ProcessGenerator
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else
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log_assert(current_case->compare.size() == 0);
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current_case = backup_case;
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current_case_assigned_bits = std::move(backup_assigned_bits);
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subst_lvalue_map.restore();
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subst_rvalue_map.restore();
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@ -714,8 +772,24 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
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this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
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removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
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// Check if any bits in lvalue have been assigned before in current_case
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bool has_overlap = false;
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for (auto &bit : this_case_eq_lvalue) {
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if (bit.wire != NULL && current_case_assigned_bits.count(bit)) {
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has_overlap = true;
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break;
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}
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}
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if (has_overlap)
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removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
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addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
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// Track newly assigned bits
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for (auto &bit : this_case_eq_lvalue)
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if (bit.wire != NULL)
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current_case_assigned_bits.insert(bit);
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}
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break;
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@ -4990,31 +4990,35 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
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other->unpack();
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}
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bool modified = false;
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bool other_modified = false;
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for (int i = GetSize(bits_) - 1; i >= 0; i--)
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{
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if (bits_[i].wire == NULL) continue;
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// Convert pattern to pool for O(1) lookup, avoiding O(n*m) chunk iteration
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pool<SigBit> pattern_bits;
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pattern_bits.reserve(pattern.size());
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for (auto &bit : pattern)
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if (bit.wire != NULL)
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pattern_bits.insert(bit);
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for (auto &pattern_chunk : pattern.chunks())
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if (bits_[i].wire == pattern_chunk.wire &&
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bits_[i].offset >= pattern_chunk.offset &&
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bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
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modified = true;
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bits_.erase(bits_.begin() + i);
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if (other != NULL) {
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other_modified = true;
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other->bits_.erase(other->bits_.begin() + i);
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}
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break;
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// Compact in-place to avoid O(n^2) erase operations
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size_t write_idx = 0;
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for (size_t read_idx = 0; read_idx < bits_.size(); read_idx++)
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{
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if (!(bits_[read_idx].wire != NULL && pattern_bits.count(bits_[read_idx]))) {
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if (write_idx != read_idx) {
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bits_[write_idx] = bits_[read_idx];
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if (other != NULL)
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other->bits_[write_idx] = other->bits_[read_idx];
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}
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write_idx++;
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}
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}
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bool modified = (write_idx < bits_.size());
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if (modified) {
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bits_.resize(write_idx);
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hash_.clear();
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try_repack();
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}
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if (other_modified) {
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if (other != NULL && modified) {
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other->bits_.resize(write_idx);
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other->hash_.clear();
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other->try_repack();
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}
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@ -5041,24 +5045,27 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
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other->unpack();
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}
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bool modified = false;
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bool other_modified = false;
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
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modified = true;
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bits_.erase(bits_.begin() + i);
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if (other != NULL) {
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other_modified = true;
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other->bits_.erase(other->bits_.begin() + i);
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// Avoid O(n^2) complexity by compacting in-place
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size_t write_idx = 0;
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for (size_t read_idx = 0; read_idx < bits_.size(); read_idx++) {
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if (!(bits_[read_idx].wire != NULL && pattern.count(bits_[read_idx]))) {
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if (write_idx != read_idx) {
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bits_[write_idx] = bits_[read_idx];
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if (other != NULL)
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other->bits_[write_idx] = other->bits_[read_idx];
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}
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write_idx++;
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}
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}
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bool modified = (write_idx < bits_.size());
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if (modified) {
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bits_.resize(write_idx);
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hash_.clear();
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try_repack();
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}
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if (other_modified) {
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if (other != NULL && modified) {
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other->bits_.resize(write_idx);
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other->hash_.clear();
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other->try_repack();
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}
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@ -5074,24 +5081,27 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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other->unpack();
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}
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bool modified = false;
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bool other_modified = false;
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
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modified = true;
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bits_.erase(bits_.begin() + i);
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if (other != NULL) {
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other_modified = true;
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other->bits_.erase(other->bits_.begin() + i);
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// Avoid O(n^2) complexity by compacting in-place
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size_t write_idx = 0;
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for (size_t read_idx = 0; read_idx < bits_.size(); read_idx++) {
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if (!(bits_[read_idx].wire != NULL && pattern.count(bits_[read_idx]))) {
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if (write_idx != read_idx) {
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bits_[write_idx] = bits_[read_idx];
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if (other != NULL)
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other->bits_[write_idx] = other->bits_[read_idx];
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}
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write_idx++;
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}
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}
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bool modified = (write_idx < bits_.size());
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if (modified) {
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bits_.resize(write_idx);
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hash_.clear();
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try_repack();
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}
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if (other_modified) {
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if (other != NULL && modified) {
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other->bits_.resize(write_idx);
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other->hash_.clear();
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other->try_repack();
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}
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333
tests/unit/kernel/sigspecRemove2Test.cc
Normal file
333
tests/unit/kernel/sigspecRemove2Test.cc
Normal file
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@ -0,0 +1,333 @@
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#include <gtest/gtest.h>
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#include "kernel/rtlil.h"
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YOSYS_NAMESPACE_BEGIN
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// Test fixture with helper functions
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class SigSpecRemove2Test : public ::testing::Test {
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protected:
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Design* d;
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Module* m;
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void SetUp() override {
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d = new Design;
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m = d->addModule("$test");
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}
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void TearDown() override {
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delete d;
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}
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// Create n wires with given width
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std::vector<Wire*> createWires(int count, int width = 4) {
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std::vector<Wire*> wires;
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for (int i = 0; i < count; i++) {
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Wire* w = m->addWire(stringf("$w%d", i), width);
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wires.push_back(w);
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}
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return wires;
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}
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// Append all wires to a SigSpec
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SigSpec wiresAsSigSpec(const std::vector<Wire*>& wires) {
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SigSpec sig;
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for (auto w : wires)
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sig.append(w);
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return sig;
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}
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// Create a SigSpec of constants
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SigSpec constsAsSigSpec(int count, int width = 4) {
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SigSpec sig;
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for (int i = 0; i < count; i++)
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sig.append(Const(i, width));
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return sig;
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}
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// Convert wires to pool of SigBits
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pool<SigBit> wiresToPool(const std::vector<Wire*>& wires) {
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pool<SigBit> pool;
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for (auto w : wires)
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for (auto &bit : SigSpec(w))
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pool.insert(bit);
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return pool;
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}
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// Convert wires to set of SigBits
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std::set<SigBit> wiresToSet(const std::vector<Wire*>& wires) {
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std::set<SigBit> set;
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for (auto w : wires)
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for (auto &bit : SigSpec(w))
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set.insert(bit);
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return set;
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}
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};
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TEST_F(SigSpecRemove2Test, WithSigSpecPattern)
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{
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auto wires = createWires(4);
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SigSpec sig = wiresAsSigSpec(wires);
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SigSpec pattern(wires[1]); // Remove w2
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SigSpec other = constsAsSigSpec(4);
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EXPECT_EQ(sig.size(), 16);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), 12);
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EXPECT_EQ(other.size(), 12);
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// Verify correct wires remain (w1, w3, w4)
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(wires[2]);
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expected.append(wires[3]);
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, WithPoolPattern)
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{
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auto wires = createWires(3);
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SigSpec sig = wiresAsSigSpec(wires);
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auto pattern = wiresToPool({wires[1]});
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SigSpec other = constsAsSigSpec(3);
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EXPECT_EQ(sig.size(), 12);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), 8);
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EXPECT_EQ(other.size(), 8);
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// Verify correct wires remain (w0, w2)
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(wires[2]);
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, WithSetPattern)
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{
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auto wires = createWires(3);
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SigSpec sig = wiresAsSigSpec(wires);
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auto pattern = wiresToSet({wires[1]});
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SigSpec other = constsAsSigSpec(3);
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EXPECT_EQ(sig.size(), 12);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), 8);
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EXPECT_EQ(other.size(), 8);
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// Verify correct wires remain (w0, w2)
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(wires[2]);
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, ManyElements)
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{
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const int num_wires = 100;
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auto wires = createWires(num_wires);
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SigSpec sig = wiresAsSigSpec(wires);
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// Remove every other wire
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std::vector<Wire*> to_remove;
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for (int i = 0; i < num_wires; i += 2)
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to_remove.push_back(wires[i]);
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auto pattern = wiresToPool(to_remove);
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EXPECT_EQ(sig.size(), num_wires * 4);
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sig.remove2(pattern, nullptr);
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EXPECT_EQ(sig.size(), (num_wires / 2) * 4);
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// Verify odd-indexed wires remain (w1, w3, w5, ..., w99)
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SigSpec expected;
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for (int i = 1; i < num_wires; i += 2)
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expected.append(wires[i]);
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EXPECT_EQ(sig, expected);
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}
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// Test remove2 with very large dataset to check scaling
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TEST_F(SigSpecRemove2Test, VeryLargeScalingTest)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires);
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SigSpec sig = wiresAsSigSpec(wires);
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SigSpec other = constsAsSigSpec(num_wires);
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// Create pattern with many chunks (one per wire)
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SigSpec pattern;
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for (int i = 0; i < num_wires; i += 2)
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pattern.append(wires[i]);
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EXPECT_EQ(sig.size(), num_wires * 4);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), (num_wires / 2) * 4);
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EXPECT_EQ(other.size(), (num_wires / 2) * 4);
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// Spot-check: odd-indexed wires should remain at expected positions
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for (int i = 0; i < num_wires / 2; i++) {
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EXPECT_EQ(sig[i * 4 + 0].wire, wires[i * 2 + 1]);
|
||||
EXPECT_EQ(sig[i * 4 + 1].wire, wires[i * 2 + 1]);
|
||||
EXPECT_EQ(sig[i * 4 + 2].wire, wires[i * 2 + 1]);
|
||||
EXPECT_EQ(sig[i * 4 + 3].wire, wires[i * 2 + 1]);
|
||||
}
|
||||
}
|
||||
|
||||
// Test multiple sequential removals (simulates removeSignalFromCaseTree)
|
||||
TEST_F(SigSpecRemove2Test, MultipleSequentialRemovals)
|
||||
{
|
||||
const int num_wires = 512;
|
||||
auto wires = createWires(num_wires);
|
||||
|
||||
// Create many actions, each with one wire
|
||||
std::vector<SigSpec> actions;
|
||||
for (auto w : wires)
|
||||
actions.push_back(SigSpec(w));
|
||||
|
||||
// Remove half the wires from all actions
|
||||
for (int i = 0; i < num_wires / 2; i++) {
|
||||
SigSpec pattern(wires[i]);
|
||||
for (auto &action : actions)
|
||||
if (action.size() > 0)
|
||||
action.remove2(pattern, nullptr);
|
||||
}
|
||||
|
||||
// Verify correct actions were cleared
|
||||
for (int i = 0; i < num_wires; i++) {
|
||||
EXPECT_EQ(actions[i].size(), i < num_wires / 2 ? 0 : 4);
|
||||
}
|
||||
|
||||
// Verify remaining actions contain the correct wires
|
||||
for (int i = num_wires / 2; i < num_wires; i++) {
|
||||
SigSpec expected(wires[i]);
|
||||
EXPECT_EQ(actions[i], expected);
|
||||
}
|
||||
}
|
||||
|
||||
// Test remove2 with very large dataset to check scaling
|
||||
TEST_F(SigSpecRemove2Test, PoolOverloadLargeDataset)
|
||||
{
|
||||
const int num_wires = 50000;
|
||||
auto wires = createWires(num_wires, 1);
|
||||
SigSpec sig = wiresAsSigSpec(wires);
|
||||
SigSpec other = constsAsSigSpec(num_wires, 1);
|
||||
|
||||
// Remove half
|
||||
pool<SigBit> pattern;
|
||||
for (int i = 0; i < num_wires; i += 2)
|
||||
pattern.insert(SigBit(wires[i], 0));
|
||||
|
||||
EXPECT_EQ(sig.size(), num_wires);
|
||||
sig.remove2(pattern, &other);
|
||||
EXPECT_EQ(sig.size(), num_wires / 2);
|
||||
EXPECT_EQ(other.size(), num_wires / 2);
|
||||
|
||||
// Spot-check: odd-indexed wires should remain
|
||||
for (int i = 0; i < num_wires / 2; i++) {
|
||||
EXPECT_EQ(sig[i].wire, wires[i * 2 + 1]);
|
||||
}
|
||||
}
|
||||
|
||||
// Test set overload (same perf characteristics as pool)
|
||||
TEST_F(SigSpecRemove2Test, SetOverloadLargeDataset)
|
||||
{
|
||||
const int num_wires = 50000;
|
||||
auto wires = createWires(num_wires, 1);
|
||||
SigSpec sig = wiresAsSigSpec(wires);
|
||||
SigSpec other = constsAsSigSpec(num_wires, 1);
|
||||
|
||||
// Remove half
|
||||
std::set<SigBit> pattern;
|
||||
for (int i = 0; i < num_wires; i += 2)
|
||||
pattern.insert(SigBit(wires[i], 0));
|
||||
|
||||
EXPECT_EQ(sig.size(), num_wires);
|
||||
sig.remove2(pattern, &other);
|
||||
EXPECT_EQ(sig.size(), num_wires / 2);
|
||||
EXPECT_EQ(other.size(), num_wires / 2);
|
||||
|
||||
// Spot-check: odd-indexed wires should remain
|
||||
for (int i = 0; i < num_wires / 2; i++) {
|
||||
EXPECT_EQ(sig[i].wire, wires[i * 2 + 1]);
|
||||
}
|
||||
}
|
||||
|
||||
// Worst case: remove almost all elements
|
||||
TEST_F(SigSpecRemove2Test, RemoveAlmostAllElements)
|
||||
{
|
||||
const int num_wires = 10000;
|
||||
auto wires = createWires(num_wires, 1);
|
||||
SigSpec sig = wiresAsSigSpec(wires);
|
||||
|
||||
// Remove all but last
|
||||
pool<SigBit> pattern;
|
||||
for (int i = 0; i < num_wires - 1; i++)
|
||||
pattern.insert(SigBit(wires[i], 0));
|
||||
|
||||
EXPECT_EQ(sig.size(), num_wires);
|
||||
sig.remove2(pattern, nullptr);
|
||||
EXPECT_EQ(sig.size(), 1);
|
||||
EXPECT_EQ(sig[0].wire, wires[num_wires - 1]);
|
||||
}
|
||||
|
||||
TEST_F(SigSpecRemove2Test, EmptyPattern)
|
||||
{
|
||||
auto wires = createWires(1);
|
||||
SigSpec sig(wires[0]);
|
||||
pool<SigBit> empty_pattern;
|
||||
|
||||
EXPECT_EQ(sig.size(), 4);
|
||||
sig.remove2(empty_pattern, nullptr);
|
||||
EXPECT_EQ(sig.size(), 4);
|
||||
|
||||
// Verify the wire is unchanged
|
||||
SigSpec expected(wires[0]);
|
||||
EXPECT_EQ(sig, expected);
|
||||
}
|
||||
|
||||
// Test that NULL wire bits (constants) are not removed
|
||||
TEST_F(SigSpecRemove2Test, NullWireBitsStay)
|
||||
{
|
||||
auto wires = createWires(1);
|
||||
SigSpec sig;
|
||||
sig.append(wires[0]);
|
||||
sig.append(Const(15, 4));
|
||||
|
||||
// Try to remove the constants
|
||||
pool<SigBit> pattern;
|
||||
SigSpec const_spec(Const(15, 4));
|
||||
for (auto &bit : const_spec)
|
||||
pattern.insert(bit);
|
||||
|
||||
EXPECT_EQ(sig.size(), 8);
|
||||
sig.remove2(pattern, nullptr);
|
||||
EXPECT_EQ(sig.size(), 8); // Constants stay
|
||||
|
||||
// Verify original content is preserved
|
||||
SigSpec expected;
|
||||
expected.append(wires[0]);
|
||||
expected.append(Const(15, 4));
|
||||
EXPECT_EQ(sig, expected);
|
||||
}
|
||||
|
||||
TEST_F(SigSpecRemove2Test, PartialBitRemoval)
|
||||
{
|
||||
Wire* w = m->addWire("$w1", 8);
|
||||
SigSpec sig(w);
|
||||
|
||||
// Remove bits 2-5
|
||||
pool<SigBit> pattern;
|
||||
for (int i = 2; i < 6; i++)
|
||||
pattern.insert(SigBit(w, i));
|
||||
|
||||
EXPECT_EQ(sig.size(), 8);
|
||||
sig.remove2(pattern, nullptr);
|
||||
EXPECT_EQ(sig.size(), 4);
|
||||
|
||||
// Verify only bits 0,1,6,7 remain
|
||||
EXPECT_EQ(sig[0], SigBit(w, 0));
|
||||
EXPECT_EQ(sig[1], SigBit(w, 1));
|
||||
EXPECT_EQ(sig[2], SigBit(w, 6));
|
||||
EXPECT_EQ(sig[3], SigBit(w, 7));
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
Loading…
Add table
Add a link
Reference in a new issue