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Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port

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muxpack: fix wide Y port handling
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Emil J 2026-03-31 10:49:39 +00:00 • committed by GitHub
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# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
read_verilog <<EOT
module top(input b, output [18:0] h);
assign h = ~|b;
endmodule
EOT
proc
muxpack