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Regression test for #5765

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Gus Smith 2026-03-30 08:59:28 -07:00
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# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
read_verilog <<EOT
module top(input b, output [18:0] h);
assign h = ~|b;
endmodule
EOT
proc
muxpack