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Clarify.

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nella 2026-04-01 08:55:20 +02:00 • committed by nella
parent b6d656e932
commit 42c309347b
2 changed files with 23 additions and 86 deletions
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65
tests/csa_tree/csa_tree_synth.ys
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@ -1,65 +0,0 @@
read_verilog <<EOT
module bench(
input [7:0] a, b, c, d, e, f, g, h,
output [7:0] y
);
assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
techmap
abc -g AND,OR,XOR
select -assert-min 236 t:$_AND_ t:$_OR_ t:$_XOR_ %u
design -reset
read_verilog <<EOT
module bench(
input [7:0] a, b, c, d, e, f, g, h,
output [7:0] y
);
assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
csa_tree
techmap
abc -g AND,OR,XOR
select -assert-max 235 t:$_AND_ t:$_OR_ t:$_XOR_ %u
design -reset
read_verilog <<EOT
module bench(
input [7:0] a, b, c, d, e, f, g, h,
output [7:0] y
);
assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
techmap
abc -D 1
select -assert-min 240 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
design -reset
read_verilog <<EOT
module bench(
input [7:0] a, b, c, d, e, f, g, h,
output [7:0] y
);
assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
opt
csa_tree
techmap
abc -D 1
select -assert-max 236 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
design -reset