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rtlil: add remove2 unit test
This commit is contained in:
Emil J. Tywoniak
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ea11453cef
commit
27737c6e2e
1 changed files with 333 additions and 0 deletions
333
tests/unit/kernel/sigspecRemove2Test.cc
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333
tests/unit/kernel/sigspecRemove2Test.cc
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#include <gtest/gtest.h>
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#include "kernel/rtlil.h"
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YOSYS_NAMESPACE_BEGIN
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// Test fixture with helper functions
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class SigSpecRemove2Test : public ::testing::Test {
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protected:
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Design* d;
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Module* m;
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void SetUp() override {
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d = new Design;
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m = d->addModule("$test");
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}
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void TearDown() override {
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delete d;
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}
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// Create n wires with given width
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std::vector<Wire*> createWires(int count, int width = 4) {
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std::vector<Wire*> wires;
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for (int i = 0; i < count; i++) {
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Wire* w = m->addWire(stringf("$w%d", i), width);
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wires.push_back(w);
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}
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return wires;
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}
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// Append all wires to a SigSpec
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SigSpec wiresAsSigSpec(const std::vector<Wire*>& wires) {
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SigSpec sig;
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for (auto w : wires)
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sig.append(w);
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return sig;
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}
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// Create a SigSpec of constants
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SigSpec constsAsSigSpec(int count, int width = 4) {
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SigSpec sig;
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for (int i = 0; i < count; i++)
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sig.append(Const(i, width));
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return sig;
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}
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// Convert wires to pool of SigBits
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pool<SigBit> wiresToPool(const std::vector<Wire*>& wires) {
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pool<SigBit> pool;
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for (auto w : wires)
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for (auto &bit : SigSpec(w))
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pool.insert(bit);
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return pool;
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}
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// Convert wires to set of SigBits
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std::set<SigBit> wiresToSet(const std::vector<Wire*>& wires) {
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std::set<SigBit> set;
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for (auto w : wires)
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for (auto &bit : SigSpec(w))
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set.insert(bit);
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return set;
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}
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};
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TEST_F(SigSpecRemove2Test, WithSigSpecPattern)
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{
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auto wires = createWires(4);
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SigSpec sig = wiresAsSigSpec(wires);
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SigSpec pattern(wires[1]); // Remove w2
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SigSpec other = constsAsSigSpec(4);
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EXPECT_EQ(sig.size(), 16);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), 12);
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EXPECT_EQ(other.size(), 12);
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// Verify correct wires remain (w1, w3, w4)
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(wires[2]);
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expected.append(wires[3]);
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, WithPoolPattern)
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{
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auto wires = createWires(3);
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SigSpec sig = wiresAsSigSpec(wires);
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auto pattern = wiresToPool({wires[1]});
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SigSpec other = constsAsSigSpec(3);
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EXPECT_EQ(sig.size(), 12);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), 8);
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EXPECT_EQ(other.size(), 8);
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// Verify correct wires remain (w0, w2)
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(wires[2]);
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, WithSetPattern)
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{
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auto wires = createWires(3);
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SigSpec sig = wiresAsSigSpec(wires);
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auto pattern = wiresToSet({wires[1]});
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SigSpec other = constsAsSigSpec(3);
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EXPECT_EQ(sig.size(), 12);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), 8);
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EXPECT_EQ(other.size(), 8);
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// Verify correct wires remain (w0, w2)
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(wires[2]);
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, ManyElements)
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{
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const int num_wires = 100;
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auto wires = createWires(num_wires);
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SigSpec sig = wiresAsSigSpec(wires);
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// Remove every other wire
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std::vector<Wire*> to_remove;
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for (int i = 0; i < num_wires; i += 2)
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to_remove.push_back(wires[i]);
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auto pattern = wiresToPool(to_remove);
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EXPECT_EQ(sig.size(), num_wires * 4);
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sig.remove2(pattern, nullptr);
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EXPECT_EQ(sig.size(), (num_wires / 2) * 4);
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// Verify odd-indexed wires remain (w1, w3, w5, ..., w99)
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SigSpec expected;
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for (int i = 1; i < num_wires; i += 2)
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expected.append(wires[i]);
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EXPECT_EQ(sig, expected);
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}
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// Test remove2 with very large dataset to check scaling
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TEST_F(SigSpecRemove2Test, VeryLargeScalingTest)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires);
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SigSpec sig = wiresAsSigSpec(wires);
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SigSpec other = constsAsSigSpec(num_wires);
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// Create pattern with many chunks (one per wire)
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SigSpec pattern;
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for (int i = 0; i < num_wires; i += 2)
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pattern.append(wires[i]);
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EXPECT_EQ(sig.size(), num_wires * 4);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), (num_wires / 2) * 4);
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EXPECT_EQ(other.size(), (num_wires / 2) * 4);
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// Spot-check: odd-indexed wires should remain at expected positions
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for (int i = 0; i < num_wires / 2; i++) {
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EXPECT_EQ(sig[i * 4 + 0].wire, wires[i * 2 + 1]);
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EXPECT_EQ(sig[i * 4 + 1].wire, wires[i * 2 + 1]);
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EXPECT_EQ(sig[i * 4 + 2].wire, wires[i * 2 + 1]);
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EXPECT_EQ(sig[i * 4 + 3].wire, wires[i * 2 + 1]);
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}
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}
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// Test multiple sequential removals (simulates removeSignalFromCaseTree)
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TEST_F(SigSpecRemove2Test, MultipleSequentialRemovals)
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{
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const int num_wires = 512;
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auto wires = createWires(num_wires);
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// Create many actions, each with one wire
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std::vector<SigSpec> actions;
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for (auto w : wires)
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actions.push_back(SigSpec(w));
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// Remove half the wires from all actions
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for (int i = 0; i < num_wires / 2; i++) {
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SigSpec pattern(wires[i]);
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for (auto &action : actions)
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if (action.size() > 0)
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action.remove2(pattern, nullptr);
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}
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// Verify correct actions were cleared
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for (int i = 0; i < num_wires; i++) {
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EXPECT_EQ(actions[i].size(), i < num_wires / 2 ? 0 : 4);
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}
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// Verify remaining actions contain the correct wires
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for (int i = num_wires / 2; i < num_wires; i++) {
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SigSpec expected(wires[i]);
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EXPECT_EQ(actions[i], expected);
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}
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}
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// Test remove2 with very large dataset to check scaling
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TEST_F(SigSpecRemove2Test, PoolOverloadLargeDataset)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires, 1);
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SigSpec sig = wiresAsSigSpec(wires);
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SigSpec other = constsAsSigSpec(num_wires, 1);
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// Remove half
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pool<SigBit> pattern;
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for (int i = 0; i < num_wires; i += 2)
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pattern.insert(SigBit(wires[i], 0));
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EXPECT_EQ(sig.size(), num_wires);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), num_wires / 2);
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EXPECT_EQ(other.size(), num_wires / 2);
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// Spot-check: odd-indexed wires should remain
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for (int i = 0; i < num_wires / 2; i++) {
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EXPECT_EQ(sig[i].wire, wires[i * 2 + 1]);
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}
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}
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// Test set overload (same perf characteristics as pool)
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TEST_F(SigSpecRemove2Test, SetOverloadLargeDataset)
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{
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const int num_wires = 50000;
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auto wires = createWires(num_wires, 1);
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SigSpec sig = wiresAsSigSpec(wires);
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SigSpec other = constsAsSigSpec(num_wires, 1);
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// Remove half
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std::set<SigBit> pattern;
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for (int i = 0; i < num_wires; i += 2)
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pattern.insert(SigBit(wires[i], 0));
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EXPECT_EQ(sig.size(), num_wires);
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sig.remove2(pattern, &other);
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EXPECT_EQ(sig.size(), num_wires / 2);
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EXPECT_EQ(other.size(), num_wires / 2);
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// Spot-check: odd-indexed wires should remain
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for (int i = 0; i < num_wires / 2; i++) {
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EXPECT_EQ(sig[i].wire, wires[i * 2 + 1]);
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}
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}
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// Worst case: remove almost all elements
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TEST_F(SigSpecRemove2Test, RemoveAlmostAllElements)
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{
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const int num_wires = 10000;
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auto wires = createWires(num_wires, 1);
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SigSpec sig = wiresAsSigSpec(wires);
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// Remove all but last
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pool<SigBit> pattern;
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for (int i = 0; i < num_wires - 1; i++)
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pattern.insert(SigBit(wires[i], 0));
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EXPECT_EQ(sig.size(), num_wires);
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sig.remove2(pattern, nullptr);
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EXPECT_EQ(sig.size(), 1);
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EXPECT_EQ(sig[0].wire, wires[num_wires - 1]);
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}
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TEST_F(SigSpecRemove2Test, EmptyPattern)
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{
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auto wires = createWires(1);
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SigSpec sig(wires[0]);
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pool<SigBit> empty_pattern;
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EXPECT_EQ(sig.size(), 4);
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sig.remove2(empty_pattern, nullptr);
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EXPECT_EQ(sig.size(), 4);
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// Verify the wire is unchanged
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SigSpec expected(wires[0]);
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EXPECT_EQ(sig, expected);
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}
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// Test that NULL wire bits (constants) are not removed
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TEST_F(SigSpecRemove2Test, NullWireBitsStay)
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{
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auto wires = createWires(1);
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SigSpec sig;
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sig.append(wires[0]);
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sig.append(Const(15, 4));
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// Try to remove the constants
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pool<SigBit> pattern;
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SigSpec const_spec(Const(15, 4));
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for (auto &bit : const_spec)
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pattern.insert(bit);
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EXPECT_EQ(sig.size(), 8);
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sig.remove2(pattern, nullptr);
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EXPECT_EQ(sig.size(), 8); // Constants stay
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// Verify original content is preserved
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SigSpec expected;
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expected.append(wires[0]);
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expected.append(Const(15, 4));
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EXPECT_EQ(sig, expected);
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}
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TEST_F(SigSpecRemove2Test, PartialBitRemoval)
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{
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Wire* w = m->addWire("$w1", 8);
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SigSpec sig(w);
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// Remove bits 2-5
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pool<SigBit> pattern;
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for (int i = 2; i < 6; i++)
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pattern.insert(SigBit(w, i));
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EXPECT_EQ(sig.size(), 8);
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sig.remove2(pattern, nullptr);
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EXPECT_EQ(sig.size(), 4);
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// Verify only bits 0,1,6,7 remain
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EXPECT_EQ(sig[0], SigBit(w, 0));
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EXPECT_EQ(sig[1], SigBit(w, 1));
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EXPECT_EQ(sig[2], SigBit(w, 6));
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EXPECT_EQ(sig[3], SigBit(w, 7));
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}
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YOSYS_NAMESPACE_END
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