Krystine Sherwin
134da811f7
Add raise_error pass
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Raise errors from attributes for testing.
I want it for bugpoint tests but it could be useful elsewhere.
2025-07-29 11:39:50 +12:00
KrystalDelusion
5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error
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simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
2025-07-21 10:26:00 +12:00
Martin Povišer
9ab1946799
Merge pull request #5209 from povik/hieropt
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Start `opt_hier` to enable hierarchical optimization
2025-07-17 14:12:18 +02:00
N. Engelhardt
d009bcc9b6
Merge pull request #5198 from YosysHQ/nak/lcov
2025-07-17 11:57:58 +02:00
N. Engelhardt
fb6974dcd7
print summary of line coverage to log
2025-07-16 13:40:07 +02:00
Emil J. Tywoniak
c7a3abbcc4
libparse: LibertyExpression unit test
2025-07-15 12:53:30 +02:00
Emil J. Tywoniak
e960428587
unit tests: fix run failure detection
2025-07-15 12:21:01 +02:00
Emil J. Tywoniak
6ee01308f2
dfflibmap: show dffe inference is broken by space ANDs
2025-07-11 00:33:01 +02:00
Emil J
14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state
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dfflibmap: propagate negated next_state to output correctly
2025-07-10 19:50:02 +02:00
Emil J. Tywoniak
7fe817c52f
dfflibmap: test negated state next_state with mixed polarities
2025-07-10 18:54:43 +02:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover
2025-07-10 14:53:22 +02:00
Emil J
66035f706e
Merge pull request #5177 from YosysHQ/emil/rename-unescape
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rename: add -unescape
2025-07-08 10:45:11 +02:00
Martin Povišer
22a44e4333
Start opt_hier
2025-07-05 16:45:52 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
N. Engelhardt
8a4f465143
update test to use suggested selection for assertions
2025-07-01 11:46:27 +02:00
Krystine Sherwin
017524d7a2
tests/verific: Don't ASAN verific
2025-06-28 11:33:18 +12:00
N. Engelhardt
ef3f541501
add linecoverage command to generate lcov report from selection
2025-06-26 13:21:53 +02:00
Emil J. Tywoniak
2b659626a3
rename: add -unescape
2025-06-24 12:33:33 +02:00
Emil J. Tywoniak
73cbcffbbb
fixup! dfflibmap: propagate negated next_state to output correctly
2025-06-24 12:31:30 +02:00
Emil J. Tywoniak
778079b058
dfflibmap: propagate negated next_state to output correctly
2025-06-24 12:01:12 +02:00
George Rennie
170933ecb0
Merge pull request #5165 from georgerennie/george/opt_dff_uaf
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opt_dff: don't remove cells until all have been visited to prevent UAF
2025-06-20 23:33:26 +01:00
garytwong
834a7294b7
verilog: fix string literal regular expression ( #5187 )
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* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-06-19 12:41:18 -04:00
Krystine Sherwin
fa68299b25
tests/verific: Add chformal tests
2025-06-14 11:06:38 +12:00
Krystine Sherwin
45131f4425
chformal: Add -assert2cover option
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Also add to chformal tests.
2025-06-14 10:54:23 +12:00
KrystalDelusion
82888580ac
Merge pull request #5152 from garytwong/unique-if
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verilog: implement SystemVerilog unique/unique0/priority if semantics.
2025-06-13 09:56:53 +12:00
Emil J
c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector
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splitnets: handle single-bit vectors consistently
2025-06-11 22:47:48 +02:00
George Rennie
7160c91800
tests: add test for #5164 opt_dff -sat UAF
2025-06-06 23:46:23 +01:00
Emil J. Tywoniak
239c265093
splitnets: handle single-bit vectors consistently
2025-06-05 10:58:06 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
George Rennie
ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
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read_verilog: fix -1 constant used to correct post increment/decrement
2025-06-04 14:22:32 +01:00
Emil J
c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs
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aiger: fix -map and -vmap
2025-06-02 15:07:19 +02:00
George Rennie
97f51bb4b7
tests: add tests for task/function argument input/output copying
2025-05-31 01:21:06 +01:00
KrystalDelusion
545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global
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SystemVerilog: Fix typedef struct in global space
2025-05-31 09:59:26 +12:00
George Rennie
3790be114f
tests: add tests for verilog pre/post increment/decrement in expressions
2025-05-30 14:38:25 +01:00
Gary Wong
7b09dc31af
tests: add cases covering full_case and parallel_case semantics
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This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.
(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
2025-05-29 20:45:57 -06:00
George Rennie
3ef4c91c31
Merge pull request #5148 from georgerennie/george/convertible_to_int_fix
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Fix convertible_to_int handling of 32 bit unsigned ints with MSB set.
2025-05-29 10:33:12 +01:00
KrystalDelusion
489a12d6c1
Merge pull request #5141 from garytwong/unique-if
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Accept (and ignore) SystemVerilog unique/priority if.
2025-05-27 09:45:50 +12:00
George Rennie
353fd0f7f4
tests: test opt_expr for 32 bit unsigned shifts
2025-05-26 15:28:44 +01:00
Krystine Sherwin
995a893afd
Tests: Add svtypes/typedef_struct_global.ys
2025-05-26 12:16:58 +12:00
Gary Wong
73e45d29d6
Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
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The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.
These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical. But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
2025-05-24 08:44:04 -06:00
Emil J
18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose
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libcache: add -quiet and -verbose
2025-05-24 00:05:46 +02:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Gary Wong
9770ece187
Accept (and ignore) SystemVerilog unique/priority if.
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Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.
This affects only the grammar accepted; the behaviour of conditionals
is not changed. (But accepting this syntax will provide scope for
possible optimisations as future work.)
Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
2025-05-22 19:28:28 -06:00
George Rennie
6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl
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opt_expr: fix shift optimization with overflowing shift amount
2025-05-22 15:16:19 +01:00
KrystalDelusion
4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst
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Update fstlib
2025-05-16 09:22:52 +12:00
KrystalDelusion
f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole
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cutpoint: Re-add whole module optimization
2025-05-16 09:22:28 +12:00
Emil J
3823157c25
Merge pull request #5080 from akashlevy/muldiv_c
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Add `muldiv_c` peepopt
2025-05-15 11:03:25 +02:00
Emil J. Tywoniak
e5171d6aa1
verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Krystine Sherwin
afd5bbc7fa
fstdata.cc: Fix last step
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Includes test file for sanity checking simulation steps.
2025-05-12 13:18:19 +12:00
