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Tests: Add svtypes/typedef_struct_global.ys

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Krystine Sherwin 2025-05-26 12:16:58 +12:00
parent 209df95fb9
commit 995a893afd
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tests/svtypes/typedef_struct_global.ys Normal file
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read_verilog -sv << EOF
typedef struct packed {
logic y;
logic x;
} Vec_2_B;
module top;
Vec_2_B two_dee;
wire foo = two_dee.x;
endmodule
EOF