Merge pull request #5198 from YosysHQ/nak/lcov

tests/various/lcov.gold

@@ -0,0 +1,44 @@
+SF:lcov.v
+DA:2,1
+DA:3,1
+DA:4,1
+DA:5,1
+DA:6,1
+DA:7,1
+DA:8,1
+DA:9,0
+DA:13,1
+DA:14,1
+DA:17,1
+DA:18,1
+DA:19,1
+DA:21,0
+DA:22,0
+DA:23,0
+DA:24,0
+DA:25,0
+DA:26,0
+DA:27,0
+DA:28,0
+DA:29,0
+DA:30,0
+DA:32,1
+DA:33,1
+DA:36,0
+DA:37,0
+DA:38,0
+DA:40,0
+DA:41,0
+DA:42,0
+DA:43,0
+DA:44,0
+DA:45,0
+DA:46,0
+DA:48,0
+DA:49,0
+DA:52,1
+DA:53,0
+DA:56,1
+LF:40
+LH:16
+end_of_record

tests/various/lcov.v

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+module top (
+    input  wire        clk,
+    input  wire        rst,
+    input  wire [7:0]  a,
+    input  wire [7:0]  b,
+    input  wire [3:0]  c,
+    input  wire        en,
+    output wire [7:0]  out1,
+    output wire [7:0]  out2
+);
+
+    // Shared intermediate signal
+    wire [7:0] ab_sum;
+    assign ab_sum = a + b;
+
+    // Logic cone for out1
+    wire [7:0] cone1_1, cone1_2;
+    assign cone1_1 = ab_sum ^ {4{c[1:0]}};
+    assign cone1_2 = (a & b) | {4{c[3:2]}};
+
+    reg  [7:0] reg1, reg2; // only reg1 feeds into out1, but both share a source location
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            reg1 <= 8'h00;
+            reg2 <= 8'hFF;
+        end else if (en) begin
+            reg1 <= cone1_1 + cone1_2;
+            reg2 <= cone1_2 - cone1_1;
+        end
+    end
+
+    wire [7:0] cone1_3;
+    assign cone1_3 = reg1 & ~a[0];
+
+    // Logic cone for out2
+    wire [7:0] cone2_1, cone2_2;
+    assign cone2_1 = (ab_sum << 1) | (a >> 2);
+    assign cone2_2 = (b ^ {4{c[2:0]}}) & 8'hAA;
+
+    reg  [7:0] reg3;
+    always @(posedge clk or posedge rst) begin
+        if (rst)
+            reg3 <= 8'h0F;
+        else
+            reg3 <= cone2_1 ^ cone2_2 ^ reg1[7:0];
+    end
+
+    wire [7:0] cone2_3;
+    assign cone2_3 = reg3 | (reg2 ^ 8'h55);
+
+    // Outputs
+    assign out1 = cone1_3 | (reg1 ^ 8'hA5);
+    assign out2 = cone2_3 & (reg3 | 8'h5A);
+
+    always @(posedge clk) begin
+        assert (out1 == 8'h42);
+    end
+
+endmodule

tests/various/lcov.ys

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+read_verilog -formal lcov.v
+prep -top top
+async2sync
+chformal -lower
+select -set covered t:$assert %ci*
+select -set irrelevant o:* %ci* %n
+linecoverage -lcov lcov.out @covered @irrelevant %u
+exec -expect-return 0 -- diff -q lcov.out lcov.gold