Start opt_hier

tests/opt/opt_hier.tcl

@@ -0,0 +1,34 @@
+yosys -import
+
+# per each opt_hier_*.v source file, confirm flattening and hieropt+flattening
+# are combinationally equivalent
+foreach fn [glob opt_hier_*.v] {
+	log -header "Test $fn"
+	log -push
+	design -reset
+
+	read_verilog $fn
+	hierarchy -auto-top
+	prep -top top
+	design -save start
+	flatten
+	design -save gold
+	design -load start
+	opt -hier
+	# check any instances marked `should_get_optimized_out` were
+	# indeed optimized out
+	select -assert-none a:should_get_optimized_out
+	dump
+	flatten
+	design -save gate
+
+	design -reset
+	design -copy-from gold -as gold A:top
+	design -copy-from gate -as gate A:top
+	yosys rename -hide
+	equiv_make gold gate equiv
+	equiv_induct equiv
+	equiv_status -assert equiv
+
+	log -pop
+}

tests/opt/opt_hier_simple1.v

@@ -0,0 +1,8 @@
+module m(input a, output y1, output y2);
+	assign y1 = a;
+	assign y2 = a;
+endmodule
+
+module top(input a, output y2, output y1);
+	m inst(.a(a), .y1(y1), .y2(y2));
+endmodule

tests/opt/opt_hier_simple2.v

@@ -0,0 +1,7 @@
+module m(input [3:0] i, output [3:0] y);
+	assign y = i + 1;
+endmodule
+
+module top(output [3:0] y);
+	m inst(.i(4), .y(y));
+endmodule

tests/opt/opt_hier_test1.v

@@ -0,0 +1,22 @@
+(* blackbox *)
+module bb(output y);
+endmodule
+
+// all instances of `m` tie together a[1], a[2]
+// this can be used to conclude y[0]=0
+module m(input [3:0] a, output [1:0] y, output x);
+	assign y[0] = a[1] != a[2];
+	assign x = a[0] ^ a[3];
+	(* should_get_optimized_out *)
+	bb bb1(.y(y[1]));
+endmodule
+
+module top(input j, output z, output [2:0] x);
+	wire [1:0] y1;
+	wire [1:0] y2;
+	wire [1:0] y3;
+	m inst1(.a(0), .y(y1), .x(x[0]));
+	m inst2(.a(15), .y(y2), .x(x[1]));
+	m inst3(.a({1'b1, j, j, 1'b0}), .y(y3), .x(x[2]));
+	assign z = (&y1) ^ (&y2) ^ (&y3);
+endmodule

tests/opt/run-test.sh

@@ -1,4 +1,4 @@
 #!/usr/bin/env bash
 set -eu
 source ../gen-tests-makefile.sh
-generate_mk --yosys-scripts
+generate_mk --yosys-scripts --tcl-scripts