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Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state
dfflibmap: propagate negated next_state to output correctly
This commit is contained in:
Emil J
GitHub
commit
14aad097f0
6 changed files with 244 additions and 2 deletions
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@ -392,9 +392,21 @@ static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_ty
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol))
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continue;
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol) || cell_set_pol != setpol)
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol))
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol))
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continue;
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if (!cell_next_pol) {
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// next_state is negated
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// we later propagate this inversion to the output,
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// which requires the swap of set and reset
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std::swap(cell_set_pin, cell_clr_pin);
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std::swap(cell_set_pol, cell_clr_pol);
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}
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if (cell_set_pol != setpol)
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continue;
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if (cell_clr_pol != clrpol)
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continue;
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std::map<std::string, char> this_cell_ports;
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@ -432,12 +444,14 @@ static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_ty
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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// next_state negation propagated to output
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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// next_state negation propagated to output
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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found_noninv_output = true;
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@ -81,3 +81,19 @@ clean
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select -assert-count 0 t:dffn
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select -assert-count 5 t:dffsr
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select -assert-count 1 t:dffe
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design -load orig
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dfflibmap -liberty dfflibmap.lib -liberty dfflibmap_dffsr_mixedpol.lib -dont_use dffsr
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clean
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# We have one more _NOT_ than with the regular dffsr
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select -assert-count 6 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr_mixedpol
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select -assert-count 1 t:dffe
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# The additional NOT is on ff2.
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# Originally, ff2.R is an active high "set".
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# dffsr_mixedpol has functionally swapped labels due to the next_state inversion,
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# so we use its CLEAR port for the "set",
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# but we have to invert it because the CLEAR pin is active low.
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# ff2.CLEAR = !R
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select -assert-count 1 c:ff2 %x:+[CLEAR] %ci t:$_NOT_ %i
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33
tests/techmap/dfflibmap_dffr_not_next.lib
Normal file
33
tests/techmap/dfflibmap_dffr_not_next.lib
Normal file
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@ -0,0 +1,33 @@
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library(test) {
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cell (dffr_not_next) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "!D";
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clocked_on : "CLK";
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clear : "CLEAR";
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preset : "PRESET";
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clear_preset_var1 : L;
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clear_preset_var2 : L;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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35
tests/techmap/dfflibmap_dffsr_mixedpol.lib
Normal file
35
tests/techmap/dfflibmap_dffsr_mixedpol.lib
Normal file
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@ -0,0 +1,35 @@
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library(test) {
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cell (dffsr_mixedpol) {
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area : 6;
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ff("IQ", "IQN") {
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// look here
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next_state : "!D";
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clocked_on : "CLK";
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// look here
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clear : "!CLEAR";
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preset : "PRESET";
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clear_preset_var1 : L;
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clear_preset_var2 : L;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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28
tests/techmap/dfflibmap_dffsr_not_next.lib
Normal file
28
tests/techmap/dfflibmap_dffsr_not_next.lib
Normal file
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@ -0,0 +1,28 @@
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library (test_not_next) {
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cell (dffsr_not_next) {
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area : 1.0;
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pin (Q) {
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direction : output;
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function : "STATE";
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}
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pin (CLK) {
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clock : true;
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direction : input;
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}
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pin (D) {
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direction : input;
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}
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pin (RN) {
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direction : input;
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}
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pin (SN) {
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direction : input;
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}
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ff (STATE,STATEN) {
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clear : "!SN";
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clocked_on : "CLK";
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next_state : "!D";
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preset : "!RN";
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}
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}
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}
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116
tests/techmap/dfflibmap_formal.ys
Normal file
116
tests/techmap/dfflibmap_formal.ys
Normal file
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@ -0,0 +1,116 @@
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##################################################################
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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// Formal checking of directly instantiated DFFSR doesn't work at the moment
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// likely due to an equiv_induct assume bug #5196
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// // Workaround for DFFSR bug #5194
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// assume property (~R || ~S);
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// $_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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// $_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffn_dffe.lib
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read_liberty dfflibmap_dffsr_not_next.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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##################################################################
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design -reset
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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// Formal checking of directly instantiated DFFSR doesn't work at the moment
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// likely due to an equiv_induct assume bug #5196
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// // Workaround for DFFSR bug #5194
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// assume property (~R || ~S);
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// $_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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// $_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffr_not_next.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffr_not_next.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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##################################################################
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design -reset
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read_verilog <<EOT
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module top(input C, D, E, S, R, output Q);
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// DFFSR with priority R over S
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always @(posedge C, posedge R, posedge S)
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if (R == 1)
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Q <= 0;
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else if (S == 1)
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Q <= 1;
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else
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Q <= D;
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffn_dffe.lib
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read_liberty dfflibmap_dffsr_not_next.lib
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copy top top_unmapped
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simplemap top
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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