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update test to use suggested selection for assertions

This commit is contained in:
N. Engelhardt 2025-07-01 11:33:03 +02:00
parent ef3f541501
commit 8a4f465143
3 changed files with 12 additions and 3 deletions

View file

@ -38,6 +38,7 @@ DA:48,0
DA:49,0
DA:52,1
DA:53,0
LF:39
DA:56,1
LF:40
LH:24
end_of_record

View file

@ -52,4 +52,8 @@ module top (
assign out1 = cone1_3 | (reg1 ^ 8'hA5);
assign out2 = cone2_3 & (reg3 | 8'h5A);
always @(posedge clk) begin
assert (out1 == 8'h42);
end
endmodule

View file

@ -1,4 +1,8 @@
read_verilog lcov.v
read_verilog -formal lcov.v
prep -top top
linecoverage -lcov lcov.out o:\out1 %ci*
async2sync
chformal -lower
select -set covered t:$assert %ci*
select -set irrelevant o:* %ci* %n
linecoverage -lcov lcov.out @covered @irrelevant %u
exec -expect-return 0 -- diff -q lcov.out lcov.gold