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Merge pull request #5148 from georgerennie/george/convertible_to_int_fix
Fix convertible_to_int handling of 32 bit unsigned ints with MSB set.
This commit is contained in:
commit
3ef4c91c31
2 changed files with 65 additions and 13 deletions
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@ -383,7 +383,23 @@ int RTLIL::Const::as_int(bool is_signed) const
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bool RTLIL::Const::convertible_to_int(bool is_signed) const
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{
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auto size = get_min_size(is_signed);
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return (size > 0 && size <= 32);
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if (size <= 0)
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return false;
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// If it fits in 31 bits it is definitely convertible
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if (size <= 31)
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return true;
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// If it fits in 32 bits, it is convertible if signed or if unsigned and the
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// leading bit is not 1
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if (size == 32) {
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if (is_signed)
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return true;
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return get_bits().at(31) != State::S1;
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}
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return false;
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}
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std::optional<int> RTLIL::Const::try_as_int(bool is_signed) const
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@ -439,18 +455,7 @@ void RTLIL::Const::compress(bool is_signed)
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std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
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{
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auto size = get_min_size(is_signed);
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if(size == 0 || size > 32)
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return std::nullopt;
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int32_t ret = 0;
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for (auto i = 0; i < size && i < 32; i++)
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if ((*this)[i] == State::S1)
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ret |= 1 << i;
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if (is_signed && (*this)[size-1] == State::S1)
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for (auto i = size; i < 32; i++)
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ret |= 1 << i;
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return ret;
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return try_as_int(is_signed);
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}
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std::string RTLIL::Const::as_string(const char* any) const
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@ -111,3 +111,50 @@ select -assert-none t:$shr
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select -assert-none t:$sshl
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select -assert-none t:$sshr
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select -assert-none t:$shiftx
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design -reset
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read_verilog <<EOT
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module top (
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input wire [3:0] in,
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output wire [7:0] shl,
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output wire [7:0] shr,
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output wire [7:0] sshl,
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output wire [7:0] sshr,
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output wire [7:0] shiftx,
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output wire [7:0] shl_s,
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output wire [7:0] shr_s,
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output wire [7:0] sshl_s,
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output wire [7:0] sshr_s,
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output wire [7:0] shiftx_s,
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);
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assign shl = in << 32'hffffffff;
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assign shr = in >> 32'hffffffff;
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assign sshl = in <<< 32'hffffffff;
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assign sshr = in >>> 32'hffffffff;
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assign shiftx = in[32'hffffffff +: 8];
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wire signed [31:0] shamt = 32'hffffffff;
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assign shl_s = in << shamt;
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assign shr_s = in >> shamt;
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assign sshl_s = in <<< shamt;
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assign sshr_s = in >>> shamt;
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assign shiftx_s = in[shamt +: 8];
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endmodule
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EOT
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select -assert-count 2 t:$shl
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select -assert-count 2 t:$shr
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select -assert-count 2 t:$sshl
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select -assert-count 2 t:$sshr
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select -assert-count 1 t:$shiftx
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equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$shl
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select -assert-none t:$shr
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select -assert-none t:$sshl
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select -assert-none t:$sshr
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select -assert-none t:$shiftx
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