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Merge pull request #5089 from YosysHQ/krys/cutpoint_whole

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cutpoint: Re-add whole module optimization
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KrystalDelusion 2025-05-16 09:22:28 +12:00 • committed by GitHub
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14
passes/sat/cutpoint.cc
View file

@ -86,6 +86,20 @@ struct CutpointPass : public Pass {
for (auto module : design->all_selected_modules())
{
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))
module->remove(cell);
vector<Wire*> output_wires;
for (auto wire : module->wires())
if (wire->port_output)
output_wires.push_back(wire);
for (auto wire : output_wires)
module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
continue;
}
SigMap sigmap(module);
pool<SigBit> cutpoint_bits;

50
tests/various/cutpoint_whole.ys Normal file
View file

@ -0,0 +1,50 @@
read_verilog << EOT
module top(input a, b, output o);
wire c, d, e;
bb bb1 (.a (a), .b (b), .o (c));
sub_mod sub_inst (.a (a), .b (b), .o (e));
some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
endmodule
(* blackbox *)
module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
endmodule
module sub_mod(input a, b, output o);
bb bb2 (.a (a), .b (b), .o (o));
endmodule
module some_mod(input a, b, c, output o);
assign o = a & (b | c);
endmodule
EOT
hierarchy -top top
design -stash hier
# removing cell
design -load hier
logger -expect log "Removing cell .*, making all cell outputs cutpoints" 1
cutpoint sub_mod/bb2
logger -check-expected
logger -werror "Removing cell .*, making all cell outputs cutpoints"
# removing wires
design -load hier
logger -expect log "Making wire .* a cutpoint" 1
cutpoint top/c
logger -check-expected
logger -werror "Making wire .* a cutpoint"
# removing output wires
design -load hier
logger -expect log "Making output wire .* a cutpoint" 1
cutpoint sub_mod/o
logger -check-expected
logger -werror "Making output wire .* a cutpoint"
# whole module optimization, doesn't do any of the previous
design -load hier
logger -expect log "Making all outputs of module .* cut points, removing module contents" 1
cutpoint sub_mod
logger -check-expected