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Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
read_verilog: fix -1 constant used to correct post increment/decrement
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commit
ab40403d90
2 changed files with 70 additions and 1 deletions
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@ -336,7 +336,8 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AS
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log_assert(stmt->type == AST_ASSIGN_EQ);
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AstNode *expr = stmt->children[0]->clone();
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if (undo) {
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AstNode *minus_one = AstNode::mkconst_int(-1, true, 1);
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AstNode *one = AstNode::mkconst_int(1, false, 1);
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AstNode *minus_one = new AstNode(AST_NEG, one);
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expr = new AstNode(op, expr, minus_one);
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}
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SET_AST_NODE_LOC(expr, begin, end);
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68
tests/verilog/incdec.ys
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68
tests/verilog/incdec.ys
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@ -0,0 +1,68 @@
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# From https://github.com/YosysHQ/yosys/issues/5151
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read_verilog -sv <<EOT
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module expr_postsub_comb (
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input logic [7:0] in_val_m2,
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input logic [7:0] sub_val_m2,
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output logic [7:0] out_diff_m2,
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output logic [7:0] var_out_m2
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);
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logic [7:0] var_m2;
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always_comb begin
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var_m2 = in_val_m2;
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out_diff_m2 = (var_m2--) - sub_val_m2;
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var_out_m2 = var_m2;
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end
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always_comb assert(out_diff_m2 == in_val_m2 - sub_val_m2);
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endmodule
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EOT
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prep
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chformal -lower
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sat -prove-asserts -verify
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design -reset
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read_verilog -sv <<EOT
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module top(
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input logic [7:0] a,
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output logic [7:0] pre_inc,
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output logic [7:0] pre_dec,
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output logic [7:0] post_inc,
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output logic [7:0] post_dec
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);
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logic [7:0] a_pre_inc, a_pre_dec, a_post_inc, a_post_dec;
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always_comb begin
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a_pre_inc = a;
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a_pre_dec = a;
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a_post_inc = a;
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a_post_dec = a;
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pre_inc = ++a_pre_inc;
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pre_dec = --a_pre_dec;
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post_inc = a_post_inc++;
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post_dec = a_post_dec--;
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end
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wire [7:0] a_inc = a + 1;
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wire [7:0] a_dec = a - 1;
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always_comb begin
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assert(a_pre_inc == a_inc);
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assert(a_pre_dec == a_dec);
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assert(a_post_inc == a_inc);
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assert(a_post_dec == a_dec);
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assert(pre_inc == a_inc);
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assert(pre_dec == a_dec);
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assert(post_inc == a);
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assert(post_dec == a);
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end
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endmodule
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EOT
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prep
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chformal -lower
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sat -prove-asserts -verify
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