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fstdata.cc: Fix last step

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Includes test file for sanity checking simulation steps.
This commit is contained in:
Krystine Sherwin 2025-05-12 13:18:19 +12:00
parent d0b9a0cb98
commit afd5bbc7fa
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2 changed files with 53 additions and 2 deletions
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4
kernel/fstdata.cc
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@ -261,12 +261,12 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
fstReaderSetUnlimitedTimeRange(ctx);
fstReaderSetFacProcessMaskAll(ctx);
fstReaderIterBlocks2(ctx, reconstruct_clb_attimes, reconstruct_clb_varlen_attimes, this, nullptr);
if (last_time!=end_time && curr_cycle < last_cycle) {
if (last_time!=end_time && curr_cycle <= last_cycle) {
past_data = last_data;
callback(last_time);
curr_cycle++;
}
if (curr_cycle < last_cycle) {
if (curr_cycle <= last_cycle) {
past_data = last_data;
callback(end_time);
curr_cycle++;

51
tests/sim/sim_cycles.ys Normal file
View file

@ -0,0 +1,51 @@
read_verilog dff.v
prep
# create fst with 20 clock cycles (41 samples, 202ns)
sim -clock clk -fst sim_cycles.fst -n 20
logger -expect-no-warnings
# final step is 41
logger -expect log "Co-simulating cycle 41" 2
logger -warn "Co-simulating cycle 42"
sim -clock clk -r sim_cycles.fst -scope dff -n 21 -sim-cmp
sim -clock clk -r sim_cycles.fst -scope dff -stop 202 -sim-cmp
logger -check-expected
# over limit stops at final step
logger -expect log "Co-simulating cycle 41" 2
sim -clock clk -r sim_cycles.fst -scope dff -n 30 -sim-cmp
# -stop warns for over limit
logger -nowarn "Stop time is after simulation file end time"
sim -clock clk -r sim_cycles.fst -scope dff -stop 300 -sim-cmp
logger -check-expected
# don't auto step last
logger -expect log "Co-simulating cycle 40" 2
logger -warn "Co-simulating cycle 41"
sim -clock clk -r sim_cycles.fst -scope dff -n 20 -sim-cmp
sim -clock clk -r sim_cycles.fst -scope dff -stop 200 -sim-cmp
logger -check-expected
# -n 10 == -stop 100
# should simulate up to 20 and not more
logger -expect log "Co-simulating cycle 20" 2
logger -warn "Co-simulating cycle 21"
sim -clock clk -r sim_cycles.fst -scope dff -n 10 -sim-cmp
sim -clock clk -r sim_cycles.fst -scope dff -stop 100 -sim-cmp
logger -check-expected
# -n 1 == -stop 10
logger -expect log "Co-simulating cycle 2" 2
logger -warn "Co-simulating cycle 3"
sim -clock clk -r sim_cycles.fst -scope dff -n 1 -sim-cmp
sim -clock clk -r sim_cycles.fst -scope dff -stop 10 -sim-cmp
logger -check-expected
# -n 0 == -stop 0
logger -expect log "Co-simulating cycle 0" 2
logger -warn "Co-simulating cycle 1"
sim -clock clk -r sim_cycles.fst -scope dff -n 0 -sim-cmp
sim -clock clk -r sim_cycles.fst -scope dff -stop 0 -sim-cmp
logger -check-expected