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Merge pull request #5095 from YosysHQ/emil/one-bit-width

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rtlil: enable single-bit vector wires
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Emil J 2025-05-23 15:55:45 +02:00 • committed by GitHub
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tests/verilog/sbvector.ys Normal file
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@ -0,0 +1,30 @@
read_verilog <<EOT
module foo(
output o,
input [0:0] i1,
input i2
);
wire [0:0] w1 = i1 ^ i2;
wire w2 = ~i1;
assign o = w1 ^ w2;
endmodule
EOT
hierarchy
proc
select -assert-count 1 w:i1
select -assert-count 1 w:i1 a:single_bit_vector %i
select -assert-count 1 w:i2
select -assert-count 0 w:i2 a:single_bit_vector %i
select -assert-count 1 w:w1
select -assert-count 1 w:w1 a:single_bit_vector %i
select -assert-count 1 w:w2
select -assert-count 0 w:w2 a:single_bit_vector %i
write_verilog verilog_sbvector.out
!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
!grep -qF 'input [0:0] i1;' verilog_sbvector.out
!grep -qF 'wire i2;' verilog_sbvector.out
!grep -qF 'input i2;' verilog_sbvector.out
!grep -qF 'wire [0:0] w1;' verilog_sbvector.out
!grep -qF 'wire w2;' verilog_sbvector.out