2090 commits

Author	SHA1	Message	Date
Clifford Wolf	153d3dd4e0	Various cleanups in synth_xilinx command	2015-01-13 13:20:32 +01:00
Clifford Wolf	1d96277f5d	Added add_share_file Makefile macro	2015-01-08 00:23:18 +01:00
Clifford Wolf	38dfc5c580	added minimalistic xilinx sim models	2015-01-08 00:05:11 +01:00
Clifford Wolf	d1e38693d5	More Xilinx bram cleanups	2015-01-07 01:59:36 +01:00
Clifford Wolf	584c5f3937	Cleanups in xilinx bram descriptions	2015-01-07 01:28:18 +01:00
Clifford Wolf	08c13f635c	Xilinx RAMB36/RAMB18 memory_bram support complete	2015-01-06 23:54:33 +01:00
Clifford Wolf	ec2eef89fa	Towards Xilinx bram support	2015-01-06 23:21:52 +01:00
Clifford Wolf	7cc5192125	small fix in xilinx/brams.v	2015-01-06 17:21:18 +01:00
Clifford Wolf	9474928672	Towards Xilinx bram support	2015-01-06 15:26:33 +01:00
Clifford Wolf	4a0b3a5423	Various small improvements to synth_xilinx	2015-01-06 14:37:50 +01:00
Clifford Wolf	081e1a49f8	Towards Xilinx bram support	2015-01-06 14:26:51 +01:00
Clifford Wolf	9c7f47bbd5	Towards Xilinx bram support	2015-01-06 13:33:51 +01:00
Clifford Wolf	9ea2511fe8	Towards Xilinx bram support	2015-01-05 13:59:04 +01:00
Clifford Wolf	8898897f7b	Towards Xilinx bram support	2015-01-04 14:23:30 +01:00
Clifford Wolf	a7e43ae3d9	Progress in memory_bram	2015-01-03 10:57:01 +01:00
Clifford Wolf	90f4017703	Added proper clkpol support to memory_bram	2015-01-02 22:57:08 +01:00
Clifford Wolf	474831643c	New $mem simlib model	2015-01-02 17:11:31 +01:00
Clifford Wolf	327a5d42b6	Progress in memory_bram	2014-12-31 22:50:08 +01:00
Clifford Wolf	94e6b70736	Added memory_bram (not functional yet)	2014-12-31 16:53:53 +01:00
Clifford Wolf	ba43cf5807	Fixed simlib entries for $memrd and $memwr	2014-12-30 13:33:29 +01:00
Clifford Wolf	c64b1de11d	Fixed build with SMALL=1	2014-12-30 11:41:24 +01:00
Clifford Wolf	4aa9fbbf3f	Improvements in simplemap api, added $ne $nex $eq $eqx support	2014-12-24 10:49:24 +01:00
Clifford Wolf	72f500c950	Removed UTF-8 chars from techmap.v	2014-12-12 12:44:16 +01:00
Clifford Wolf	f1764b4fe9	Added $dffe cell type	2014-12-08 10:50:19 +01:00
Clifford Wolf	fad9cec47b	Added $_DFFE_??_ cell types	2014-12-08 10:43:38 +01:00
Clifford Wolf	74ef92b9c8	Added "abc" label in synth script	2014-10-31 03:46:27 +01:00
Clifford Wolf	ab28491f27	Added "opt -full" alias for all more aggressive optimizations	2014-10-31 03:36:51 +01:00
Clifford Wolf	c3e779a65f	Added $_BUF_ cell type	2014-10-03 10:12:28 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	4888d61c65	Improvements in "synth" script	2014-09-18 12:57:55 +02:00
Clifford Wolf	6644e27cd4	Fixed $macc simlib model for zero-config	2014-09-16 08:19:35 +02:00
Clifford Wolf	7815f81c32	Added "synth" command	2014-09-14 16:09:06 +02:00
Clifford Wolf	923bbbeaf0	Using alumacc in techmap.v	2014-09-14 14:50:15 +02:00
Clifford Wolf	44b5bd4b63	Fixed simlib $macc model for xilinx xsim	2014-09-08 17:09:39 +02:00
Clifford Wolf	fcb46138ce	Simplified $fa undef model	2014-09-08 16:59:39 +02:00
Clifford Wolf	6dc07eb1f2	Fixes and cleanups for blackbox.v	2014-09-08 13:31:04 +02:00
Clifford Wolf	af0c8873bb	Added $lcu cell type	2014-09-08 13:31:04 +02:00
Clifford Wolf	d46bac3305	Added "$fa" cell type	2014-09-08 12:15:39 +02:00
Clifford Wolf	dd887cc025	Using maccmap for $macc and $mul techmap	2014-09-07 18:24:08 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	fa64942018	Added $macc SAT model	2014-09-06 19:44:11 +02:00
Clifford Wolf	bff4706b62	Added $macc simlib model (also use as techmap rule for now)	2014-09-06 17:59:12 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	635b922afe	Undef-related fixes in simlib $alu model	2014-09-02 23:21:59 +02:00
Clifford Wolf	c38283dbd0	Small bug fixes in $not, $neg, and $shiftx models	2014-09-02 17:48:41 +02:00
Clifford Wolf	9923762461	Fixed "test_cell -simlib all"	2014-09-01 15:37:56 +02:00
Clifford Wolf	8649b57b6f	Added $lut support in test_cell, techmap, satgen	2014-08-31 17:43:31 +02:00
Clifford Wolf	4724d94fbc	Added $alu cell type	2014-08-30 18:59:05 +02:00
Clifford Wolf	eb571cba6a	Replaced $__alu CO/CS outputs with full-width CO output	2014-08-30 15:12:39 +02:00
Clifford Wolf	a92a68ce52	Using "via_celltype" in $mul carry-save-acc implementation	2014-08-18 14:30:20 +02:00