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Added $dffe cell type

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Clifford Wolf 2014-12-08 10:50:19 +01:00
parent fad9cec47b
commit f1764b4fe9
4 changed files with 54 additions and 1 deletions
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19
techlibs/common/simlib.v
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@ -1216,6 +1216,25 @@ end
endmodule
// --------------------------------------------------------
module \$dffe (CLK, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
input CLK, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
if (EN == EN_POLARITY) Q <= D;
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR

2
techlibs/common/techmap.v
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@ -59,7 +59,7 @@ module _90_simplemap_various;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
module _90_simplemap_registers;
endmodule