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Improvements in simplemap api, added $ne $nex $eq $eqx support

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Clifford Wolf 2014-12-24 10:49:24 +01:00
parent edb3c9d0c4
commit 4aa9fbbf3f
4 changed files with 112 additions and 75 deletions
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54
techlibs/common/techmap.v
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@ -53,6 +53,11 @@ endmodule
module _90_simplemap_logic_ops;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$eq $eqx $ne $nex" *)
module _90_simplemap_compare_ops;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$pos $slice $concat $mux" *)
module _90_simplemap_various;
@ -406,55 +411,6 @@ module _90_pow (A, B, Y);
endmodule
// --------------------------------------------------------
// Equal and Not-Equal
// --------------------------------------------------------
(* techmap_celltype = "$eq $eqx" *)
module _90_eq_eqx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
(* techmap_celltype = "$ne $nex" *)
module _90_ne_nex (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
// Parallel Multiplexers
// --------------------------------------------------------