mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Simplified $fa undef model

Browse source
This commit is contained in:
Clifford Wolf 2014-09-08 16:59:39 +02:00
parent 6dc07eb1f2
commit fcb46138ce
3 changed files with 6 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/common/simlib.v
View file

@ -453,7 +453,7 @@ output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
assign Y = t1 ^ C, X = t2 | t3;
assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
endmodule