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Cleanups in xilinx bram descriptions
This commit is contained in:
Clifford Wolf
parent
b26590f8ab
commit
584c5f3937
2 changed files with 36 additions and 36 deletions
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@ -209,8 +209,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[15:0]),
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.DOPADOP(DOP[1:0]),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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@ -219,8 +219,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI[15:0]),
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.DIPBDIP(DIP[1:0]),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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@ -251,8 +251,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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wire [13:0] A1ADDR_14 = {A1ADDR, 3'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 3'b0};
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [8:0] A1DATA_BUF;
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reg [8:0] B1DATA_Q;
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@ -268,8 +268,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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@ -282,7 +282,7 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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@ -292,8 +292,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI({8'b0, DI}),
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.DIPBDIP({1'b0, DIP}),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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@ -324,8 +324,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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wire [13:0] A1ADDR_14 = {A1ADDR, 2'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 2'b0};
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [3:0] A1DATA_BUF;
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reg [3:0] B1DATA_Q;
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@ -341,8 +341,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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@ -355,7 +355,7 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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@ -365,8 +365,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI({8'b0, DI}),
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.DIPBDIP({1'b0, DIP}),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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@ -397,8 +397,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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wire [13:0] A1ADDR_14 = {A1ADDR, 1'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 1'b0};
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [3:0] A1DATA_BUF;
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reg [3:0] B1DATA_Q;
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@ -414,8 +414,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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@ -428,7 +428,7 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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@ -438,8 +438,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI({8'b0, DI}),
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.DIPBDIP({1'b0, DIP}),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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@ -470,8 +470,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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wire [13:0] A1ADDR_14 = A1ADDR;
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wire [13:0] B1ADDR_14 = B1ADDR;
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wire DIP, DOP;
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wire [7:0] DI, DO;
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [3:0] A1DATA_BUF;
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reg [3:0] B1DATA_Q;
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@ -487,8 +487,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
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assign A1DATA_BUF = { DOP, DO };
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assign { DIP, DI } = B1DATA;
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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@ -501,7 +501,7 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[7:0]),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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@ -511,8 +511,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI({8'b0, DI}),
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.DIPBDIP({1'b0, DIP}),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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@ -83,16 +83,16 @@ module bram1_tb #(
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xorshift64_next;
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clk <= 0;
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for (i = 0; i < 256; i = i+1) begin
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for (i = 0; i < 512; i = i+1) begin
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if (DBITS > 64)
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WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
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else
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WR_DATA <= xorshift64_state;
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xorshift64_next;
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WR_ADDR <= getaddr(i[7:4]);
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WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
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xorshift64_next;
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RD_ADDR <= getaddr(i[3:0]);
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WR_EN <= ^i;
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RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
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WR_EN <= xorshift64_state[55];
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xorshift64_next;
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#1; clk <= 1;
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