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Added proper clkpol support to memory_bram

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Clifford Wolf 2015-01-02 22:45:26 +01:00
parent 1dca7ae486
commit 90f4017703
3 changed files with 34 additions and 6 deletions
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2
techlibs/common/simlib.v
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@ -1539,7 +1539,7 @@ function port_active;
end
endfunction
always @* begin
always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
for (i = 0; i < RD_PORTS; i = i+1) begin
if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];