mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Progress in memory_bram

Browse source
This commit is contained in:
Clifford Wolf 2015-01-03 10:57:01 +01:00
parent 146f769bee
commit a7e43ae3d9
5 changed files with 25 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

3
techlibs/common/simlib.v
View file

@ -1540,6 +1540,9 @@ function port_active;
endfunction
always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
`ifdef SIMLIB_MEMDELAY
#`SIMLIB_MEMDELAY;
`endif
for (i = 0; i < RD_PORTS; i = i+1) begin
if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];