mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Removed $bu0 cell type

Browse source
This commit is contained in:
Clifford Wolf 2014-09-04 02:07:52 +02:00
parent b9cb483f3e
commit 8927aa6148
18 changed files with 27 additions and 103 deletions
Download patch file Download diff file Expand all files Collapse all files

24
techlibs/common/simlib.v
View file

@ -53,30 +53,6 @@ endgenerate
endmodule
// --------------------------------------------------------
module \$bu0 (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1
assign Y[A_WIDTH-1:0] = A;
assign Y[Y_WIDTH-1:A_WIDTH] = 0;
end else if (A_SIGNED) begin:BLOCK2
assign Y = $signed(A);
end else begin:BLOCK3
assign Y = A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$pos (A, Y);

15
techlibs/common/techmap.v
View file

@ -38,11 +38,6 @@
// Use simplemap for trivial cell types
// --------------------------------------------------------
(* techmap_simplemap *)
(* techmap_celltype = "$pos $bu0" *)
module simplemap_buffers;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$not $and $or $xor $xnor" *)
module simplemap_bool_ops;
@ -59,7 +54,7 @@ module simplemap_logic_ops;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$slice $concat $mux" *)
(* techmap_celltype = "$pos $slice $concat $mux" *)
module simplemap_various;
endmodule
@ -738,8 +733,8 @@ module \$eq (A, B, Y);
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
@ -759,8 +754,8 @@ module \$ne (A, B, Y);
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule