add a simulator #3

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programmerjake merged 58 commits from adding-simulator into master 2024-12-16 04:06:48 +00:00

Conversation 2 Commits 58 Files changed 50 +31883 -149

programmerjake commented 2024-11-20 21:27:13 +00:00

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I figured i should probably make a PR...

I figured i should probably make a PR...

programmerjake added 12 commits 2024-11-20 21:27:13 +00:00

WIP adding simulator 56ff69ba52

WIP implementing simulator 32253bc3f4

add missing copyright headers 41ce9b3474

working on simulator 96b3f1fee4

working on simulator 5b2abd3fca

working on simulator... f780e31622

simulator WIP: use petgraph for topological sort over assignments d7d8e2e7ce

Simulation::settle_step() works for simple modules 2e9d5c1835

simple combinatorial simulation works! 414a2d74f1

WIP adding VCD output 6eef3c23b5

wire up simulator trace writing interface 904752fa0c

WIP adding VCD output 16ea6850c8

programmerjake force-pushed adding-simulator from 16ea6850c8 to e2653a3245 2024-11-21 06:37:04 +00:00 Compare

programmerjake force-pushed adding-simulator from e2653a3245 to 11ddbc43c7 2024-11-21 06:54:27 +00:00 Compare

programmerjake added 1 commit 2024-11-23 00:07:45 +00:00

WIP adding deduce_resets pass 913baa37e9

programmerjake added 1 commit 2024-11-24 11:44:55 +00:00

WIP working on implementing deduce_resets pass 59be3bd645

programmerjake added 1 commit 2024-11-24 22:39:57 +00:00

working on deduce_resets pass 698b8adc23

programmerjake added 1 commit 2024-11-24 22:42:54 +00:00

increase rust version to support omitting match arms with uninhabited types 52ab134673

programmerjake added 1 commit 2024-11-24 22:46:47 +00:00

increase rust version in CI too 9516fe03a1

programmerjake added 2 commits 2024-11-25 08:01:28 +00:00

update petgraph dependency to include UnionFind::new_set() fa50930ff8

working on deduce_resets 3e3da53bd2

programmerjake added 1 commit 2024-11-26 08:07:27 +00:00

working on deduce_resets.rs 7851bf545c

programmerjake added 2 commits 2024-11-27 04:48:41 +00:00

add ResetType to the list of recognized type bounds 89d84551f8

make ClockDomain and Reg generic over reset type 9b5f1218fd

programmerjake added 1 commit 2024-11-27 05:27:15 +00:00

working on deduce_resets 546010739a

programmerjake added 1 commit 2024-11-27 05:28:50 +00:00

Merge remote-tracking branch 'origin/master' into adding-simulator 9128a84284

programmerjake added 2 commits 2024-11-27 09:32:53 +00:00

add more expr casts 358cdd10c8

working on deduce_resets d744d85c66

programmerjake added 2 commits 2024-11-28 07:24:29 +00:00

make ToReset generic over the reset type d36cf92d7f

deduce_resets works! 6446b71afd

programmerjake added 1 commit 2024-11-28 07:52:29 +00:00

simulating circuits with deduced resets works 3abba7f9eb

programmerjake added 4 commits 2024-12-02 04:14:51 +00:00

deduce_resets: show more debugging info on assertion failure 965fe53077

add some ExprCastTo supertraits to ResetType to make generic code easier 12b3ba57f1

vcd: single bit signals have no spaces in their value changes 5e0548db26

sim: add support for registers fd45465d35

programmerjake added 1 commit 2024-12-02 04:26:40 +00:00

test doc tests in CI d3f52292a1

programmerjake commented 2024-12-02 04:36:05 +00:00

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got simulating circuits with registers to work! only things left: enums and memories and a few kinds of expressions

got simulating circuits with registers to work! only things left: enums and memories and a few kinds of expressions

programmerjake added 1 commit 2024-12-03 05:06:43 +00:00

WIP adding enums to simulator 4422157db8

programmerjake added 2 commits 2024-12-05 04:59:26 +00:00

impl ToExpr for TargetBase 15bc304bb6

sim: implement enums (except for connecting unequal enum types) 42afd2da0e

programmerjake added 1 commit 2024-12-05 05:04:47 +00:00

vcd: handle enums with fields 643816d5b5

programmerjake added 1 commit 2024-12-06 02:17:31 +00:00

tests/sim: split expected output text into separate files 259bee39c2

programmerjake added 2 commits 2024-12-06 04:32:49 +00:00

change to version 0.3.0 for breaking change 9f42cab471

add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference e504cfebfe

programmerjake added 1 commit 2024-12-06 05:35:42 +00:00

sim: WIP adding memory support 3ed7827485

programmerjake added 1 commit 2024-12-06 23:53:57 +00:00

sim: WIP working on memory 9654167ca3

programmerjake added 2 commits 2024-12-10 07:03:40 +00:00

change memory write latency to NonZeroUsize to match read latency being usize cd0dd7b7ee

sim: implement memories, still needs testing e4cf66adf8

programmerjake commented 2024-12-10 07:14:50 +00:00

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I think this should be complete enough to merge once I add tests for enums and memories.

there are a few missing minor features still that I probably won't implement before merging:

• proper implementation of connect when connecting enum types that aren't the same type -- e.g. connecting HdlOption<UInt<2>> with HdlOption<UInt<5>>. (tbh I think that's a mis-feature in FIRRTL). it already should work fine for connecting identical enum types (which is what I expect people to use almost exclusively).
• simulating external modules -- maybe they'll be more inputs/outputs for the simulation?
• simulating formal assume/assert/cover -- assume/assert are simple enough, cover can probably be ignored
• handling ReadWrite memory ports with ReadUnderWrite::Old and/or non-equal read/write latencies -- blocked on: https://github.com/chipsalliance/firrtl-spec/issues/263 -- the semantics are not as expected, so I'm making sure I implement the right semantics. ReadWrite memory ports with ReadUnderWrite::New/ReadUnderWrite::Undefined and equal read/write latencies should work.
• optimizing the generated instructions to not use bigints for nearly everything

I think this should be complete enough to merge once I add tests for enums and memories. there are a few missing minor features still that I probably won't implement before merging: * proper implementation of connect when connecting enum types that aren't the same type -- e.g. connecting `HdlOption<UInt<2>>` with `HdlOption<UInt<5>>`. (tbh I think that's a mis-feature in FIRRTL). it already should work fine for connecting identical enum types (which is what I expect people to use almost exclusively). * simulating external modules -- maybe they'll be more inputs/outputs for the simulation? * simulating formal assume/assert/cover -- assume/assert are simple enough, cover can probably be ignored * handling ReadWrite memory ports with `ReadUnderWrite::Old` and/or non-equal read/write latencies -- blocked on: https://github.com/chipsalliance/firrtl-spec/issues/263 -- the semantics are not as expected, so I'm making sure I implement the right semantics. ReadWrite memory ports with `ReadUnderWrite::New`/`ReadUnderWrite::Undefined` and equal read/write latencies should work. * optimizing the generated instructions to not use bigints for nearly everything

programmerjake added 3 commits 2024-12-11 07:41:28 +00:00

tests/sim: add WIP test for enums ca759168ff

sim/vcd: fix variable identifiers to follow verilog rules 564ccb30bc

sim: add .dot output for Assignments graph for debugging 6b31e6d515

programmerjake added 2 commits 2024-12-11 08:01:41 +00:00

sim: fix assignments graph by properly including conditions as assignment inputs 5087f16099

tests/sim: test_enums works! 8616ee4737

programmerjake added 1 commit 2024-12-12 07:29:06 +00:00

sim: add WIP memory test 393f78a14d

programmerjake added 2 commits 2024-12-13 00:27:48 +00:00

sim/interpreter: fix StatePartLayout name in debug output 562c479b62

sim/interpreter: add addresses to instruction listing 8d030ac65d

programmerjake added 1 commit 2024-12-13 03:48:21 +00:00

sim: simple memory test works! 903ca1bf30

programmerjake added 1 commit 2024-12-13 04:51:12 +00:00

tests/sim: add test for memory rw port c756aeec70

programmerjake added 1 commit 2024-12-13 23:05:23 +00:00

add more memory tests 2af38de900

programmerjake added 1 commit 2024-12-13 23:07:26 +00:00

Merge remote-tracking branch 'origin/master' into adding-simulator 304d8da0e8

programmerjake changed title from WIP: add a simulator to add a simulator 2024-12-16 04:06:22 +00:00

programmerjake merged commit 304d8da0e8 into master 2024-12-16 04:06:48 +00:00

programmerjake deleted branch adding-simulator 2024-12-16 04:06:49 +00:00

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Reference: libre-chip/fayalite#3

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