fayalite

switch ready_valid::queue formal proofs to use formal_global_clock

test.yml #395 -Commit ffca1a279d pushed by programmerjake

master

2026-06-05 08:13:36 +00:00

4m47s

switch ready_valid::queue formal proofs to use formal_global_clock

test.yml #394 -Commit ffca1a279d pushed by programmerjake

#77

2026-06-05 08:01:39 +00:00

4m16s

switch ready_valid::queue formal proofs to use formal_global_clock

test.yml #393 -Commit e7ee1e862e pushed by programmerjake

#77

2026-06-05 07:52:09 +00:00

3m10s

fayalite/src/module: check that expressions are visible where they are used, e.g. erroring when a wire is inside an `if` but used outside.

test.yml #392 -Commit 31353862ce pushed by programmerjake

master

2026-06-02 08:36:33 +00:00

4m55s

fayalite/src/module: check that expressions are visible where they are used, e.g. erroring when a wire is inside an `if` but used outside.

test.yml #391 -Commit 31353862ce pushed by programmerjake

#76

2026-06-02 08:30:31 +00:00

4m21s

non-working build on TLII (using QEMU for x86 binaries)

test.yml #390 -Commit fd2c635343 pushed by HaeckseAlex

tp/rebase2

2026-05-24 18:56:09 +00:00

20s

Add .to_trace_as_string() and clean up code

test.yml #389 -Commit cf3e6cfc6b pushed by programmerjake

master

2026-05-15 05:27:48 +00:00

4m46s

Add .to_trace_as_string() and clean up code

test.yml #388 -Commit cf3e6cfc6b pushed by programmerjake

#75

2026-05-15 05:17:51 +00:00

4m10s

Add .to_trace_as_string() and clean up code

test.yml #387 -Commit cefccab47c pushed by programmerjake

#75

2026-05-15 05:08:21 +00:00

1m1s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

test.yml #386 -Commit ea183eac87 pushed by programmerjake

master

2026-05-14 02:53:13 +00:00

4m54s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

test.yml #385 -Commit ea183eac87 pushed by programmerjake

#74

2026-05-14 02:48:15 +00:00

4m16s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

test.yml #384 -Commit 299cbfa348 pushed by programmerjake

#74

2026-05-14 02:42:58 +00:00

1m42s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

test.yml #383 -Commit 36c348e01c pushed by programmerjake

#74

2026-05-14 02:38:36 +00:00

3m11s

sim: properly update all VCD wires when they share simulation state

test.yml #382 -Commit 26224abe1c pushed by programmerjake

master

2026-05-06 04:27:05 +00:00

4m42s

sim: properly update all VCD wires when they share simulation state

test.yml #381 -Commit 26224abe1c pushed by programmerjake

#73

2026-05-06 04:22:19 +00:00

4m9s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

test.yml #380 -Commit 2266315944 pushed by programmerjake

master

2026-05-04 06:38:15 +00:00

4m43s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

test.yml #379 -Commit 2266315944 pushed by programmerjake

#72

2026-05-04 06:33:28 +00:00

7m18s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

test.yml #378 -Commit 7e9d7739fb pushed by programmerjake

master

2026-05-02 02:00:27 +00:00

4m41s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

test.yml #377 -Commit 7e9d7739fb pushed by programmerjake

#71

2026-05-02 01:55:40 +00:00

4m7s

add support for custom debug/display formatting of #[hdl] structs/enums

test.yml #376 -Commit 8e4eeef723 pushed by programmerjake

master

2026-05-01 06:23:14 +00:00

4m42s

add support for custom debug/display formatting of #[hdl] structs/enums

test.yml #375 -Commit 8e4eeef723 pushed by programmerjake

#70

2026-05-01 06:18:29 +00:00

4m7s

sim: Speed up updating traces by tracking which traces are written to

test.yml #374 -Commit 402f457c68 pushed by programmerjake

master

2026-05-01 02:23:30 +00:00

4m48s

sim: Speed up updating traces by tracking which traces are written to

test.yml #373 -Commit 402f457c68 pushed by programmerjake

#69

2026-05-01 02:18:37 +00:00

4m11s

Run Rocq tests.

test.yml #372 -Commit 8cff3687f7 pushed by cesar

master

2026-03-31 00:27:46 +00:00

4m59s

Run Rocq tests.

test.yml #371 -Commit 8cff3687f7 pushed by cesar

#64

2026-03-30 22:47:14 +00:00

8m7s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

test.yml #370 -Commit 80b92c7dd3 pushed by programmerjake

master

2026-03-27 02:24:13 +00:00

4m55s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

test.yml #369 -Commit 80b92c7dd3 pushed by programmerjake

#68

2026-03-27 02:19:14 +00:00

4m18s

add simulator tests for queue()

test.yml #368 -Commit 2aa41137d4 pushed by programmerjake

master

2026-03-25 06:48:49 +00:00

5m3s

add simulator tests for queue()

test.yml #367 -Commit 2aa41137d4 pushed by programmerjake

#67

2026-03-25 06:43:42 +00:00

8m0s

update ui test's expected output for having rust-src available

test.yml #366 -Commit a93e66d8ab pushed by programmerjake

master

2026-03-18 03:59:45 +00:00

4m58s