Add .to_trace_as_string() and clean up code
test.yml #389 -Commit
cf3e6cfc6b
pushed by
programmerjake
Add .to_trace_as_string() and clean up code
test.yml #388 -Commit
cf3e6cfc6b
pushed by
programmerjake
Add .to_trace_as_string() and clean up code
test.yml #387 -Commit
cefccab47c
pushed by
programmerjake
add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
test.yml #386 -Commit
ea183eac87
pushed by
programmerjake
add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
test.yml #385 -Commit
ea183eac87
pushed by
programmerjake
add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
test.yml #384 -Commit
299cbfa348
pushed by
programmerjake
add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
test.yml #383 -Commit
36c348e01c
pushed by
programmerjake
sim: properly update all VCD wires when they share simulation state
test.yml #382 -Commit
26224abe1c
pushed by
programmerjake
sim: properly update all VCD wires when they share simulation state
test.yml #381 -Commit
26224abe1c
pushed by
programmerjake
redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
test.yml #380 -Commit
2266315944
pushed by
programmerjake
redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
test.yml #379 -Commit
2266315944
pushed by
programmerjake
use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option
test.yml #378 -Commit
7e9d7739fb
pushed by
programmerjake
use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option
test.yml #377 -Commit
7e9d7739fb
pushed by
programmerjake
add support for custom debug/display formatting of #[hdl] structs/enums
test.yml #376 -Commit
8e4eeef723
pushed by
programmerjake
add support for custom debug/display formatting of #[hdl] structs/enums
test.yml #375 -Commit
8e4eeef723
pushed by
programmerjake
sim: Speed up updating traces by tracking which traces are written to
test.yml #374 -Commit
402f457c68
pushed by
programmerjake
sim: Speed up updating traces by tracking which traces are written to
test.yml #373 -Commit
402f457c68
pushed by
programmerjake
change vcd output to have module contents under instance's name, more closely matching how it works in verilog
test.yml #370 -Commit
80b92c7dd3
pushed by
programmerjake
change vcd output to have module contents under instance's name, more closely matching how it works in verilog
test.yml #369 -Commit
80b92c7dd3
pushed by
programmerjake
update ui test's expected output for having rust-src available
test.yml #366 -Commit
a93e66d8ab
pushed by
programmerjake
update ui test's expected output for having rust-src available
test.yml #365 -Commit
a93e66d8ab
pushed by
programmerjake
change VCD id generation to be based on hashing the path, making them better for git diff
test.yml #364 -Commit
dbed947408
pushed by
programmerjake
change VCD id generation to be based on hashing the path, making them better for git diff
test.yml #363 -Commit
dbed947408
pushed by
programmerjake
speed up simulation by optimizing SimulationImpl::read_traces
test.yml #360 -Commit
c632e5d570
pushed by
programmerjake