add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
test.yml #233 -Commit
3458c21f44
pushed by
programmerjake
add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
test.yml #232 -Commit
3458c21f44
pushed by
programmerjake
support unknown trait bounds in type parameters
test.yml #231 -Commit
cdd84953d0
pushed by
programmerjake
support unknown trait bounds in type parameters
test.yml #230 -Commit
cdd84953d0
pushed by
programmerjake
add #[hdl] let destructuring and, while at it, tuple patterns
test.yml #229 -Commit
86a1bb46be
pushed by
programmerjake
add #[hdl] let destructuring and, while at it, tuple patterns
test.yml #228 -Commit
86a1bb46be
pushed by
programmerjake
sim: fix "label address not set" bug when the last Assignment is conditional
test.yml #227 -Commit
d4ea826051
pushed by
programmerjake
sim: fix "label address not set" bug when the last Assignment is conditional
test.yml #226 -Commit
d4ea826051
pushed by
programmerjake
properly handle duplicate names in vcd
test.yml #223 -Commit
e3a2ccd41c
pushed by
programmerjake
properly handle duplicate names in vcd
test.yml #222 -Commit
e3a2ccd41c
pushed by
programmerjake
Gather the FIFO debug ports in a bundle
test.yml #221 -Commit
3771cea78e
pushed by
programmerjake
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
test.yml #218 -Commit
c16726cee6
pushed by
programmerjake
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
test.yml #217 -Commit
c16726cee6
pushed by
programmerjake
WIP implementing handling #[cfg] and #[cfg_attr] in proc macro inputs
test.yml #214 -Commit
b7ec623bfa
pushed by
programmerjake
WIP implementing handling #[cfg] and #[cfg_attr] in proc macro inputs
test.yml #213 -Commit
9dc16bc73b
pushed by
programmerjake
Add assertions and debug ports in order for the FIFO to pass induction
test.yml #210 -Commit
ad1101934c
pushed by
cesar
Initial queue formal proof based on one-entry FIFO equivalence
test.yml #209 -Commit
fef7fea3ea
pushed by
cesar
make sim::Compiler not print things to stdout unless you ask for it
test.yml #208 -Commit
9b06019bf5
pushed by
programmerjake
make sim::Compiler not print things to stdout unless you ask for it
test.yml #207 -Commit
9b06019bf5
pushed by
programmerjake
sim: fix sim.write to struct
test.yml #204 -Commit
36bad52978
pushed by
programmerjake