simple combinatorial simulation works!
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2e9d5c1835
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414a2d74f1
SSH key fingerprint:
SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
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@ -227,12 +227,29 @@ macro_rules! impl_int {
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impl<Width: Size> BoolOrIntType for $name<Width> {
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type Width = Width;
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type Signed = ConstBool<$SIGNED>;
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type Value = $value<Width>;
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fn width(self) -> usize {
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$name::width(self)
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}
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fn new(width: Width::SizeType) -> Self {
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$name { width }
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}
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fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value {
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$value::<Width>::from_bigint_wrapping(self, v)
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}
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fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
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#[derive(Copy, Clone, Eq, PartialEq, Hash)]
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struct MemoizeBitsToValue;
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impl Memoize for MemoizeBitsToValue {
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type Input = BitSlice;
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type InputOwned = BitVec;
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type Output = Arc<BitVec>;
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fn inner(self, input: &Self::Input) -> Self::Output {
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Arc::new(input.to_bitvec())
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}
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}
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$value::new(MemoizeBitsToValue.get_cow(bits))
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}
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fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
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#[derive(Copy, Clone, Eq, PartialEq, Hash)]
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struct MemoizeBitsToExpr;
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@ -334,6 +351,24 @@ macro_rules! impl_int {
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}
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}
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impl<Width: Size> PartialOrd for $value<Width> {
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fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
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Some(self.cmp(other))
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}
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}
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impl<Width: Size> Ord for $value<Width> {
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fn cmp(&self, other: &Self) -> std::cmp::Ordering {
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self.to_bigint().cmp(&other.to_bigint())
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}
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}
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impl<Width: Size> From<$value<Width>> for BigInt {
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fn from(v: $value<Width>) -> BigInt {
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v.to_bigint()
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}
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}
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impl<Width: Size> $value<Width> {
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pub fn width(&self) -> usize {
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if let Some(retval) = Width::KNOWN_VALUE {
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@ -482,6 +517,19 @@ macro_rules! impl_prim_int {
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$(#[$meta:meta])*
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$prim_int:ident, $ty:ty
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) => {
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impl From<$prim_int> for <$ty as BoolOrIntType>::Value {
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fn from(v: $prim_int) -> Self {
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<$ty>::le_bytes_to_value_wrapping(
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&v.to_le_bytes(),
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<$ty as BoolOrIntType>::Width::VALUE,
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)
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}
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}
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impl From<NonZero<$prim_int>> for <$ty as BoolOrIntType>::Value {
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fn from(v: NonZero<$prim_int>) -> Self {
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v.get().into()
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}
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}
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$(#[$meta])*
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impl ToExpr for $prim_int {
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type Type = $ty;
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@ -498,10 +546,7 @@ macro_rules! impl_prim_int {
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type Type = $ty;
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fn to_expr(&self) -> Expr<Self::Type> {
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<$ty>::le_bytes_to_expr_wrapping(
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&self.get().to_le_bytes(),
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<$ty as BoolOrIntType>::Width::VALUE,
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)
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self.get().to_expr()
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}
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}
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};
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@ -531,6 +576,15 @@ impl_prim_int!(
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pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
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type Width: Size;
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type Signed: GenericConstBool;
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type Value: Clone
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+ Ord
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+ std::hash::Hash
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+ fmt::Debug
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+ Send
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+ Sync
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+ 'static
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+ ToExpr<Type = Self>
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+ Into<BigInt>;
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fn width(self) -> usize;
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fn new(width: <Self::Width as Size>::SizeType) -> Self;
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fn new_static() -> Self
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@ -545,6 +599,10 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
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fn as_same_width_uint(self) -> UIntType<Self::Width> {
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UIntType::new(Self::Width::from_usize(self.width()))
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}
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fn value_from_int_wrapping(self, v: impl Into<BigInt>) -> Self::Value {
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self.value_from_bigint_wrapping(v.into())
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}
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fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value;
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fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
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let width = self.width();
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let mut bytes = v.to_signed_bytes_le();
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@ -567,8 +625,9 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
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BitSlice::<u8, Lsb0>::from_slice_mut(&mut bytes)[..bits.len()].clone_from_bitslice(bits);
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BigInt::from_signed_bytes_le(&bytes)
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}
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fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value;
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fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self>;
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fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
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fn le_bytes_to_bits_wrapping(bytes: &[u8], bit_width: usize) -> BitVec {
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let bitslice = BitSlice::<u8, Lsb0>::from_slice(bytes);
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let bitslice = &bitslice[..bit_width.min(bitslice.len())];
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let mut bits = BitVec::new();
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@ -577,7 +636,17 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
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bit_width,
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Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false),
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);
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Self::bits_to_expr(Cow::Owned(bits))
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bits
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}
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fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
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Self::bits_to_expr(Cow::Owned(Self::le_bytes_to_bits_wrapping(
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bytes, bit_width,
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)))
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}
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fn le_bytes_to_value_wrapping(bytes: &[u8], bit_width: usize) -> Self::Value {
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Self::bits_to_value(Cow::Owned(Self::le_bytes_to_bits_wrapping(
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bytes, bit_width,
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)))
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}
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}
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@ -629,6 +698,7 @@ impl sealed::BoolOrIntTypeSealed for Bool {}
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impl BoolOrIntType for Bool {
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type Width = ConstUsize<1>;
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type Signed = ConstBool<false>;
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type Value = bool;
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fn width(self) -> usize {
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1
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@ -639,10 +709,19 @@ impl BoolOrIntType for Bool {
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Bool
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}
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fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value {
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v.bit(0)
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}
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fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
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assert_eq!(bits.len(), 1);
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bits[0].to_expr()
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}
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fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
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assert_eq!(bits.len(), 1);
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bits[0]
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}
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}
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impl Bool {
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@ -714,6 +714,18 @@ impl<T: BundleType> Instance<T> {
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source_location,
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}
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}
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pub fn from_canonical(v: Instance<Bundle>) -> Self {
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let Instance {
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scoped_name,
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instantiated,
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source_location,
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} = v;
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Self {
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scoped_name,
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instantiated: Module::from_canonical(*instantiated).intern_sized(),
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source_location,
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}
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}
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pub fn containing_module_name(self) -> Interned<str> {
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self.containing_module_name_id().0
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}
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@ -11,29 +11,33 @@ use crate::{
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GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField,
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TargetPathElement,
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},
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ExprEnum, Flow,
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ExprEnum, Flow, ToLiteralBits,
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},
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int::BoolOrIntType,
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intern::{Intern, Interned, Memoize},
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module::{
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AnnotatedModuleIO, Block, ModuleBody, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration,
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StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
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AnnotatedModuleIO, Block, Id, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt,
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StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
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StmtWire,
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},
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prelude::*,
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sim::interpreter::{
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Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
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SlotDebugData, SmallUInt, StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex,
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StatePartIndexRange, StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots,
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StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
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TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
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SlotDebugData, SmallUInt, State, StatePartArrayIndex, StatePartArrayIndexed,
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StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
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StatePartKindSmallSlots, StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex,
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TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
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},
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ty::StaticType,
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util::DebugAsDisplay,
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};
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use hashbrown::HashMap;
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use hashbrown::{HashMap, HashSet};
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use num_bigint::BigInt;
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use num_traits::ToPrimitive;
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use petgraph::visit::{
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GraphBase, IntoNeighbors, IntoNeighborsDirected, IntoNodeIdentifiers, VisitMap, Visitable,
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};
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use std::{collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
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use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
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mod interpreter;
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@ -2744,7 +2748,14 @@ impl Compiler {
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Compiled {
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insns: Insns::from(self.insns).intern_sized(),
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base_module,
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base_module_io_ty: self.base_module.io_ty(),
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io: Instance::new_unchecked(
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ScopedNameId(
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NameId("<simulator>".intern(), Id::new()),
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self.base_module.name_id(),
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),
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self.base_module,
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self.base_module.source_location(),
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),
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}
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}
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}
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@ -2758,7 +2769,7 @@ struct CompiledModule {
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pub struct Compiled<T: BundleType> {
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insns: Interned<Insns<InsnsBuildingDone>>,
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base_module: CompiledModule,
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base_module_io_ty: T,
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io: Instance<T>,
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}
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impl<T: BundleType> Compiled<T> {
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@ -2769,48 +2780,338 @@ impl<T: BundleType> Compiled<T> {
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let Self {
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insns,
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base_module,
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base_module_io_ty,
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io,
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} = self;
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Compiled {
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insns,
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base_module,
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base_module_io_ty: Bundle::from_canonical(base_module_io_ty.canonical()),
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io: Instance::from_canonical(io.canonical()),
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}
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}
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pub fn from_canonical(canonical: Compiled<Bundle>) -> Self {
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let Compiled {
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insns,
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base_module,
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base_module_io_ty,
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io,
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} = canonical;
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Self {
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insns,
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base_module,
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base_module_io_ty: T::from_canonical(base_module_io_ty.canonical()),
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io: Instance::from_canonical(io.canonical()),
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}
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}
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}
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#[derive(Debug)]
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pub struct Simulation<T: BundleType> {
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struct SimulationImpl {
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state: interpreter::State,
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base_module: CompiledModule,
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base_module_io_ty: T,
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io: Expr<Bundle>,
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uninitialized_inputs: HashSet<Target>,
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io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
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made_initial_step: bool,
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}
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impl SimulationImpl {
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fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) {
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self.io_targets.insert(target, value);
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match value.layout.body {
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CompiledTypeLayoutBody::Scalar => match target.flow() {
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Flow::Source => {}
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Flow::Sink => {
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self.uninitialized_inputs.insert(target);
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}
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Flow::Duplex => unreachable!(),
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},
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CompiledTypeLayoutBody::Array { .. } => {
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let value = value.map_ty(Array::from_canonical);
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for index in 0..value.layout.ty.len() {
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self.parse_io(
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target.join(
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TargetPathElement::from(TargetPathArrayElement { index })
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.intern_sized(),
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),
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value.element(index),
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);
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}
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}
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CompiledTypeLayoutBody::Bundle { .. } => {
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let value = value.map_ty(Bundle::from_canonical);
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for BundleField { name, .. } in value.layout.ty.fields() {
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self.parse_io(
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target.join(
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TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
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),
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value.field_by_name(name),
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);
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}
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}
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}
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}
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fn new(compiled: Compiled<Bundle>) -> Self {
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let mut retval = Self {
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state: State::new(compiled.insns),
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io: compiled.io.to_expr(),
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uninitialized_inputs: HashSet::new(),
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io_targets: HashMap::new(),
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made_initial_step: false,
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};
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let io_target = Target::from(compiled.io);
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for (BundleField { name, .. }, value) in compiled
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.io
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.ty()
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.fields()
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.into_iter()
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.zip(compiled.base_module.module_io)
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{
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retval.parse_io(
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io_target
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.join(TargetPathElement::from(TargetPathBundleField { name }).intern_sized()),
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value,
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);
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}
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retval
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}
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#[track_caller]
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fn settle_step(&mut self) {
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assert!(
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self.uninitialized_inputs.is_empty(),
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"didn't initialize all inputs",
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);
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self.state.setup_call(0);
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self.state.run();
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self.made_initial_step = true;
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}
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#[track_caller]
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fn get_io(&self, target: Target) -> CompiledValue<CanonicalType> {
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if let Some(&retval) = self.io_targets.get(&target) {
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return retval;
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}
|
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if Some(&target) == self.io.target().as_deref()
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|| Some(target.base()) != self.io.target().map(|v| v.base())
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{
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panic!("simulator read/write expression must be an array element/field of `Simulator::io()`");
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};
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panic!("simulator read/write expression must not have dynamic array indexes");
|
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}
|
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#[track_caller]
|
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fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
|
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let Some(target) = io.target() else {
|
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panic!("can't read from expression that's not a field/element of `Simulation::io()`");
|
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};
|
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let compiled_value = self.get_io(*target);
|
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if !self.made_initial_step {
|
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match target.flow() {
|
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Flow::Source => {
|
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panic!("can't read from an output before the simulation has made any steps");
|
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}
|
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Flow::Sink => {
|
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if self.uninitialized_inputs.contains(&*target) {
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panic!("can't read from an uninitialized input");
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}
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}
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Flow::Duplex => unreachable!(),
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}
|
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}
|
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match compiled_value.range.len() {
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TypeLen {
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small_slots:
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StatePartLen {
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value: 1,
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_phantom: _,
|
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},
|
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big_slots:
|
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StatePartLen {
|
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value: 0,
|
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_phantom: _,
|
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},
|
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} => Expr::ty(io).value_from_int_wrapping(
|
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self.state.small_slots[compiled_value.range.small_slots.start],
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),
|
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TypeLen {
|
||||
small_slots:
|
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StatePartLen {
|
||||
value: 0,
|
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_phantom: _,
|
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},
|
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big_slots:
|
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StatePartLen {
|
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value: 1,
|
||||
_phantom: _,
|
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},
|
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} => Expr::ty(io).value_from_int_wrapping(
|
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self.state.big_slots[compiled_value.range.big_slots.start].clone(),
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),
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_ => unreachable!(),
|
||||
}
|
||||
}
|
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#[track_caller]
|
||||
fn write_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>, value: I::Value) {
|
||||
let Some(target) = io.target() else {
|
||||
panic!("can't write to an expression that's not a field/element of `Simulation::io()`");
|
||||
};
|
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let compiled_value = self.get_io(*target);
|
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match target.flow() {
|
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Flow::Source => {
|
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panic!("can't write to an output");
|
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}
|
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Flow::Sink => {}
|
||||
Flow::Duplex => unreachable!(),
|
||||
}
|
||||
let value: BigInt = value.into();
|
||||
if !self.made_initial_step {
|
||||
self.uninitialized_inputs.remove(&*target);
|
||||
}
|
||||
match compiled_value.range.len() {
|
||||
TypeLen {
|
||||
small_slots:
|
||||
StatePartLen {
|
||||
value: 1,
|
||||
_phantom: _,
|
||||
},
|
||||
big_slots:
|
||||
StatePartLen {
|
||||
value: 0,
|
||||
_phantom: _,
|
||||
},
|
||||
} => {
|
||||
self.state.small_slots[compiled_value.range.small_slots.start] =
|
||||
value.to_u64().expect("value out of range");
|
||||
}
|
||||
TypeLen {
|
||||
small_slots:
|
||||
StatePartLen {
|
||||
value: 0,
|
||||
_phantom: _,
|
||||
},
|
||||
big_slots:
|
||||
StatePartLen {
|
||||
value: 1,
|
||||
_phantom: _,
|
||||
},
|
||||
} => self.state.big_slots[compiled_value.range.big_slots.start] = value,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Simulation<T: BundleType> {
|
||||
sim_impl: SimulationImpl,
|
||||
io: Expr<T>,
|
||||
}
|
||||
|
||||
struct SortedSetDebug<'a, T>(&'a HashSet<T>);
|
||||
|
||||
impl<T: fmt::Debug> fmt::Debug for SortedSetDebug<'_, T> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let mut entries = Vec::from_iter(self.0.iter().map(|v| {
|
||||
if f.alternate() {
|
||||
format!("{v:#?}")
|
||||
} else {
|
||||
format!("{v:?}")
|
||||
}
|
||||
}));
|
||||
entries.sort();
|
||||
f.debug_set()
|
||||
.entries(entries.iter().map(DebugAsDisplay))
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
|
||||
struct SortedMapDebug<'a, K, V>(&'a HashMap<K, V>);
|
||||
|
||||
impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let mut entries = Vec::from_iter(self.0.iter().map(|(k, v)| {
|
||||
if f.alternate() {
|
||||
(format!("{k:#?}"), format!("{v:#?}"))
|
||||
} else {
|
||||
(format!("{k:?}"), format!("{v:?}"))
|
||||
}
|
||||
}));
|
||||
entries.sort();
|
||||
f.debug_map()
|
||||
.entries(
|
||||
entries
|
||||
.iter()
|
||||
.map(|(k, v)| (DebugAsDisplay(k), DebugAsDisplay(v))),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: BundleType> fmt::Debug for Simulation<T> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let Self {
|
||||
sim_impl:
|
||||
SimulationImpl {
|
||||
state,
|
||||
io: _,
|
||||
uninitialized_inputs,
|
||||
io_targets,
|
||||
made_initial_step,
|
||||
},
|
||||
io,
|
||||
} = self;
|
||||
f.debug_struct("Simulation")
|
||||
.field("state", state)
|
||||
.field("io", io)
|
||||
.field(
|
||||
"uninitialized_inputs",
|
||||
&SortedSetDebug(uninitialized_inputs),
|
||||
)
|
||||
.field("io_targets", &SortedMapDebug(io_targets))
|
||||
.field("made_initial_step", made_initial_step)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: BundleType> Simulation<T> {
|
||||
pub fn new(module: Interned<Module<T>>) -> Self {
|
||||
Self::from_compiled(Compiled::new(module))
|
||||
}
|
||||
pub fn from_compiled(compiled: Compiled<T>) -> Self {
|
||||
Self {
|
||||
state: interpreter::State::new(compiled.insns),
|
||||
base_module: compiled.base_module,
|
||||
base_module_io_ty: compiled.base_module_io_ty,
|
||||
pub fn canonical(self) -> Simulation<Bundle> {
|
||||
let Self { sim_impl, io } = self;
|
||||
Simulation {
|
||||
sim_impl,
|
||||
io: Expr::as_bundle(io),
|
||||
}
|
||||
}
|
||||
pub fn from_canonical(canonical: Simulation<Bundle>) -> Self {
|
||||
let Simulation { sim_impl, io } = canonical;
|
||||
Self {
|
||||
sim_impl,
|
||||
io: Expr::from_bundle(io),
|
||||
}
|
||||
}
|
||||
pub fn io(&self) -> Expr<T> {
|
||||
self.io.to_expr()
|
||||
}
|
||||
pub fn from_compiled(compiled: Compiled<T>) -> Self {
|
||||
let sim_impl = SimulationImpl::new(compiled.canonical());
|
||||
Self {
|
||||
io: Expr::from_bundle(sim_impl.io),
|
||||
sim_impl,
|
||||
}
|
||||
}
|
||||
#[track_caller]
|
||||
pub fn settle_step(&mut self) {
|
||||
self.state.setup_call(0);
|
||||
self.state.run();
|
||||
self.sim_impl.settle_step();
|
||||
}
|
||||
#[track_caller]
|
||||
pub fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
|
||||
self.sim_impl.read_bool_or_int(io)
|
||||
}
|
||||
#[track_caller]
|
||||
pub fn write_bool_or_int<I: BoolOrIntType>(
|
||||
&mut self,
|
||||
io: Expr<I>,
|
||||
value: impl ToExpr<Type = I>,
|
||||
) {
|
||||
let value = value.to_expr();
|
||||
assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch");
|
||||
let value = value
|
||||
.to_literal_bits()
|
||||
.expect("the value that is being written to an input must be a literal");
|
||||
self.sim_impl
|
||||
.write_bool_or_int(io, I::bits_to_value(Cow::Borrowed(&value)));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1718,6 +1718,23 @@ impl<
|
|||
}
|
||||
}
|
||||
|
||||
impl<K: StatePartKind<State: Deref<Target: Index<usize, Output = T>>>, T> Index<StatePartIndex<K>>
|
||||
for StatePart<K>
|
||||
{
|
||||
type Output = T;
|
||||
fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
|
||||
&self.value[index.value as usize]
|
||||
}
|
||||
}
|
||||
|
||||
impl<K: StatePartKind<State: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
|
||||
IndexMut<StatePartIndex<K>> for StatePart<K>
|
||||
{
|
||||
fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
|
||||
&mut self.value[index.value as usize]
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
|
||||
Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
|
||||
{
|
||||
|
|
|
|||
|
|
@ -37,6 +37,18 @@ impl<T: Type> Wire<T> {
|
|||
ty: ty.canonical(),
|
||||
}
|
||||
}
|
||||
pub fn from_canonical(v: Wire<CanonicalType>) -> Self {
|
||||
let Wire {
|
||||
name,
|
||||
source_location,
|
||||
ty,
|
||||
} = v;
|
||||
Self {
|
||||
name,
|
||||
source_location,
|
||||
ty: T::from_canonical(ty),
|
||||
}
|
||||
}
|
||||
pub fn ty(&self) -> T {
|
||||
self.ty
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
// See Notices.txt for copyright information
|
||||
use fayalite::{prelude::*, sim::Simulation};
|
||||
use fayalite::{int::UIntValue, prelude::*, sim::Simulation};
|
||||
|
||||
#[hdl_module(outline_generated)]
|
||||
pub fn connect_const() {
|
||||
|
|
@ -70,44 +70,55 @@ fn test_connect_const() {
|
|||
],
|
||||
},
|
||||
},
|
||||
base_module: CompiledModule {
|
||||
module_io: [
|
||||
CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<8>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
|
||||
ty: UInt<8>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
io: Instance {
|
||||
name: <simulator>::connect_const,
|
||||
instantiated: Module {
|
||||
name: connect_const,
|
||||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::connect_const,
|
||||
instantiated: Module {
|
||||
name: connect_const,
|
||||
..
|
||||
},
|
||||
],
|
||||
},
|
||||
base_module_io_ty: connect_const {
|
||||
o: UInt<8>,
|
||||
}.o: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<8>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
|
||||
ty: UInt<8>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
},
|
||||
made_initial_step: true,
|
||||
}"# {
|
||||
panic!();
|
||||
}
|
||||
assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
|
||||
}
|
||||
|
||||
#[hdl_module(outline_generated)]
|
||||
|
|
@ -137,10 +148,13 @@ pub fn mod1() {
|
|||
connect(o, child);
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_mod1() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let mut sim = Simulation::new(mod1());
|
||||
sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
|
||||
sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
|
||||
sim.settle_step();
|
||||
let sim_debug = format!("{sim:#?}");
|
||||
println!("#######\n{sim_debug}\n#######");
|
||||
|
|
@ -326,199 +340,344 @@ fn test_mod1() {
|
|||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
10,
|
||||
-2,
|
||||
-2,
|
||||
15,
|
||||
10,
|
||||
-2,
|
||||
-2,
|
||||
15,
|
||||
10,
|
||||
-2,
|
||||
-2,
|
||||
15,
|
||||
-2,
|
||||
14,
|
||||
5,
|
||||
0,
|
||||
1,
|
||||
15,
|
||||
],
|
||||
},
|
||||
},
|
||||
base_module: CompiledModule {
|
||||
module_io: [
|
||||
CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 4,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(3),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
],
|
||||
},
|
||||
base_module_io_ty: mod1 {
|
||||
o: mod1_child {
|
||||
i: UInt<4>,
|
||||
o: SInt<2>,
|
||||
i2: SInt<2>,
|
||||
o2: UInt<4>,
|
||||
io: Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 4,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(3),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.i: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.i2: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.o: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.o2: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
},
|
||||
made_initial_step: true,
|
||||
}"# {
|
||||
panic!();
|
||||
}
|
||||
let expected = -2_hdl_i2;
|
||||
assert_eq!(sim.read_bool_or_int(sim.io().o.o).to_expr(), expected);
|
||||
let expected = 0xF_hdl_u4;
|
||||
assert_eq!(sim.read_bool_or_int(sim.io().o.o2).to_expr(), expected);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue