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sim/interpreter: fix StatePartLayout name in debug output

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This commit is contained in:
Jacob Lifshay 2024-12-12 15:06:17 -08:00
parent 393f78a14d
commit 562c479b62
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
8 changed files with 104 additions and 104 deletions
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2
crates/fayalite/src/sim/interpreter.rs
View file

@ -1711,7 +1711,7 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K,
layout_data,
_phantom: _,
} = self;
write!(f, "StatePartAllocationLayout<{}>", K::NAME)?;
write!(f, "StatePartLayout<{}>", K::NAME)?;
let mut debug_struct = f.debug_struct("");
debug_struct
.field("len", &debug_data.len())

10
crates/fayalite/tests/sim/expected/connect_const.txt
View file

@ -3,12 +3,12 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -23,7 +23,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -80,12 +80,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<8>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

14
crates/fayalite/tests/sim/expected/connect_const_reset.txt
View file

@ -3,12 +3,12 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 5,
debug_data: [
SlotDebugData {
@ -35,7 +35,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -109,12 +109,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -143,12 +143,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

30
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 10,
debug_data: [
SlotDebugData {
@ -72,7 +72,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -219,12 +219,12 @@ Simulation {
rst: AsyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -249,12 +249,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -276,12 +276,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -314,12 +314,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -348,12 +348,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -382,12 +382,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

30
crates/fayalite/tests/sim/expected/counter_sync.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 9,
debug_data: [
SlotDebugData {
@ -68,7 +68,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -200,12 +200,12 @@ Simulation {
rst: SyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -230,12 +230,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -257,12 +257,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -295,12 +295,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -329,12 +329,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -363,12 +363,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

46
crates/fayalite/tests/sim/expected/enums.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 5,
debug_data: [
SlotDebugData {
@ -33,7 +33,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 82,
debug_data: [
SlotDebugData {
@ -388,7 +388,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -999,12 +999,12 @@ Simulation {
rst: SyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -1029,12 +1029,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1056,12 +1056,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1094,12 +1094,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1128,12 +1128,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1162,12 +1162,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1196,12 +1196,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1230,12 +1230,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1264,12 +1264,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1298,12 +1298,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

42
crates/fayalite/tests/sim/expected/mod1.txt
View file

@ -3,12 +3,12 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 17,
debug_data: [
SlotDebugData {
@ -83,7 +83,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -237,12 +237,12 @@ Simulation {
o2: UInt<4>,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -275,12 +275,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -302,12 +302,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -329,12 +329,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -356,12 +356,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -394,12 +394,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -428,12 +428,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -462,12 +462,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -496,12 +496,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

34
crates/fayalite/tests/sim/expected/shift_register.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 13,
debug_data: [
SlotDebugData {
@ -84,7 +84,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -281,12 +281,12 @@ Simulation {
rst: SyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -311,12 +311,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -338,12 +338,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -376,12 +376,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -410,12 +410,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -444,12 +444,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -478,12 +478,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {