vcd: single bit signals have no spaces in their value changes

crates/fayalite/src/sim/vcd.rs

@@ -477,7 +477,7 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
     fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
         match value.len() {
             0 => self.writer.write_all(b"s0 ")?,
-            1 => write!(self.writer, "{} ", if value[0] { "1" } else { "0" })?,
+            1 => self.writer.write_all(if value[0] { b"1" } else { b"0" })?,
             _ => {
                 self.writer.write_all(b"b")?;
                 let mut any_ones = false;

crates/fayalite/tests/sim.rs

@@ -185,8 +185,8 @@ $var wire 1 " bit_out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-1 !
-1 "
+1!
+1"
 $end
 #1000000
 "# {