deduce_resets works!
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@ -2,7 +2,8 @@
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// See Notices.txt for copyright information
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use fayalite::{
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assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
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module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, ty::StaticType,
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module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, reset::ResetType,
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ty::StaticType,
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};
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use serde_json::json;
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@ -4026,3 +4027,263 @@ circuit check_enum_connect_any:
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",
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};
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}
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#[hdl_module(outline_generated)]
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pub fn check_deduce_resets<T: ResetType>(ty: T) {
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#[hdl]
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let cd: ClockDomain<T> = m.input(ClockDomain[ty]);
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#[hdl]
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let my_reg = reg_builder().reset(0u8).clock_domain(cd);
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#[hdl]
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let u8_in: UInt<8> = m.input();
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connect(my_reg, u8_in);
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#[hdl]
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let u8_out: UInt<8> = m.output();
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connect(u8_out, my_reg);
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#[hdl]
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let enum_in: OneOfThree<Reset, AsyncReset, SyncReset> = m.input();
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#[hdl]
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let enum_out: OneOfThree<Reset, AsyncReset, SyncReset> = m.output();
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#[hdl]
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let reset_out: Reset = m.output();
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connect(reset_out, cd.rst.to_reset());
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#[hdl]
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match enum_in {
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OneOfThree::<_, _, _>::A(v) => {
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connect(
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enum_out,
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OneOfThree[Reset][AsyncReset][SyncReset].A(cd.rst.to_reset()),
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);
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connect(reset_out, v);
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}
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OneOfThree::<_, _, _>::B(v) => {
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connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].B(v))
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}
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OneOfThree::<_, _, _>::C(v) => {
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connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].C(v))
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}
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}
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}
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#[test]
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fn test_deduce_resets() {
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let _n = SourceLocation::normalize_files_for_tests();
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let m = check_deduce_resets(Reset);
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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options: ExportOptions {
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simplify_enums: None,
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..ExportOptions::default()
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},
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"/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
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circuit check_deduce_resets:
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type Ty0 = {clk: Clock, rst: Reset}
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type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
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module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
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input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
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input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
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output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
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output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
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regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
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connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
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connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
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connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
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match enum_in: @[module-XXXXXXXXXX.rs 12:1]
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A(_match_arm_value):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
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connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
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B(_match_arm_value_1):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_2):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
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",
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};
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fayalite::module::transform::deduce_resets::deduce_resets(m.canonical().intern_sized(), false)
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.unwrap_err();
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let m = fayalite::module::transform::deduce_resets::deduce_resets(
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m.canonical().intern_sized(),
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true,
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)
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.unwrap();
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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options: ExportOptions {
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simplify_enums: None,
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..ExportOptions::default()
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},
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"/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
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circuit check_deduce_resets:
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type Ty0 = {clk: Clock, rst: UInt<1>}
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type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
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module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
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input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
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input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
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output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
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output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
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regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
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connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
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connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
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connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
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match enum_in: @[module-XXXXXXXXXX.rs 12:1]
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A(_match_arm_value):
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connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
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connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
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B(_match_arm_value_1):
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connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_2):
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connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
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",
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};
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let m = check_deduce_resets(SyncReset);
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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options: ExportOptions {
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simplify_enums: None,
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..ExportOptions::default()
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},
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"/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
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circuit check_deduce_resets:
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type Ty0 = {clk: Clock, rst: UInt<1>}
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type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
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module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
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input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
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input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
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output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
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output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
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regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
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connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
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connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
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connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
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match enum_in: @[module-XXXXXXXXXX.rs 12:1]
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A(_match_arm_value):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
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connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
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B(_match_arm_value_1):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_2):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
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",
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};
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let m = fayalite::module::transform::deduce_resets::deduce_resets(
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m.canonical().intern_sized(),
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false,
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)
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.unwrap();
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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options: ExportOptions {
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simplify_enums: None,
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..ExportOptions::default()
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},
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"/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
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circuit check_deduce_resets:
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type Ty0 = {clk: Clock, rst: UInt<1>}
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type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
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module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
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input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
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input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
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output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
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output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
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regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
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connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
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connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
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connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
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match enum_in: @[module-XXXXXXXXXX.rs 12:1]
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A(_match_arm_value):
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connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
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connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
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B(_match_arm_value_1):
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connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_2):
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connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
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",
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};
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let m = check_deduce_resets(AsyncReset);
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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options: ExportOptions {
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simplify_enums: None,
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..ExportOptions::default()
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},
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"/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
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circuit check_deduce_resets:
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type Ty0 = {clk: Clock, rst: AsyncReset}
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type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
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module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
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input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
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input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
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output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
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output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
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regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
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connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
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connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
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connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
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match enum_in: @[module-XXXXXXXXXX.rs 12:1]
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A(_match_arm_value):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
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connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
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B(_match_arm_value_1):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_2):
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connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
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",
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};
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let m = fayalite::module::transform::deduce_resets::deduce_resets(
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m.canonical().intern_sized(),
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false,
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)
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.unwrap();
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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options: ExportOptions {
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simplify_enums: None,
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..ExportOptions::default()
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},
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"/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
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circuit check_deduce_resets:
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type Ty0 = {clk: Clock, rst: AsyncReset}
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type Ty1 = {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}
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module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
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input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
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input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
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output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
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output reset_out: AsyncReset @[module-XXXXXXXXXX.rs 10:1]
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regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
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connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
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connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
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connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
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match enum_in: @[module-XXXXXXXXXX.rs 12:1]
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A(_match_arm_value):
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connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
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connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
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B(_match_arm_value_1):
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connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_2):
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connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
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",
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};
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}
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