change memory write latency to NonZeroUsize to match read latency being usize
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parent
9654167ca3
commit
cd0dd7b7ee
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@ -22,7 +22,7 @@ use std::{
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fmt,
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hash::{Hash, Hasher},
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marker::PhantomData,
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num::NonZeroU32,
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num::NonZeroUsize,
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rc::Rc,
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};
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@ -478,7 +478,7 @@ struct MemImpl<Element: Type, Len: Size, P> {
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initial_value: Option<Interned<BitSlice>>,
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ports: P,
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read_latency: usize,
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write_latency: NonZeroU32,
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write_latency: NonZeroUsize,
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read_under_write: ReadUnderWrite,
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port_annotations: Interned<[TargetedAnnotation]>,
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mem_annotations: Interned<[Annotation]>,
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@ -562,7 +562,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
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initial_value: Option<Interned<BitSlice>>,
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ports: Interned<[MemPort<DynPortType>]>,
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read_latency: usize,
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write_latency: NonZeroU32,
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write_latency: NonZeroUsize,
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read_under_write: ReadUnderWrite,
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port_annotations: Interned<[TargetedAnnotation]>,
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mem_annotations: Interned<[Annotation]>,
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@ -645,7 +645,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
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pub fn read_latency(self) -> usize {
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self.0.read_latency
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}
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pub fn write_latency(self) -> NonZeroU32 {
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pub fn write_latency(self) -> NonZeroUsize {
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self.0.write_latency
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}
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pub fn read_under_write(self) -> ReadUnderWrite {
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@ -707,7 +707,7 @@ pub(crate) struct MemBuilderTarget {
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pub(crate) initial_value: Option<Interned<BitSlice>>,
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pub(crate) ports: Vec<MemPort<DynPortType>>,
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pub(crate) read_latency: usize,
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pub(crate) write_latency: NonZeroU32,
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pub(crate) write_latency: NonZeroUsize,
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pub(crate) read_under_write: ReadUnderWrite,
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pub(crate) port_annotations: Vec<TargetedAnnotation>,
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pub(crate) mem_annotations: Vec<Annotation>,
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@ -867,7 +867,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
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initial_value: None,
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ports: vec![],
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read_latency: 0,
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write_latency: NonZeroU32::new(1).unwrap(),
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write_latency: NonZeroUsize::new(1).unwrap(),
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read_under_write: ReadUnderWrite::Old,
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port_annotations: vec![],
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mem_annotations: vec![],
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@ -1030,10 +1030,10 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
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pub fn read_latency(&mut self, read_latency: usize) {
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self.target.borrow_mut().read_latency = read_latency;
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}
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pub fn get_write_latency(&self) -> NonZeroU32 {
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pub fn get_write_latency(&self) -> NonZeroUsize {
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self.target.borrow().write_latency
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}
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pub fn write_latency(&mut self, write_latency: NonZeroU32) {
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pub fn write_latency(&mut self, write_latency: NonZeroUsize) {
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self.target.borrow_mut().write_latency = write_latency;
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}
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pub fn get_read_under_write(&self) -> ReadUnderWrite {
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