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HaeckseAlex cesar postmaster programmerjake

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HaeckseAlex

cesar

postmaster

programmerjake

sim: properly update all VCD wires when they share simulation state

#73 by programmerjake was merged 2026-05-06 04:22:21 +00:00

master

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

#72 by programmerjake was merged 2026-05-04 06:33:29 +00:00

master

implement #[hdl(cmp_eq)] for enums and use it for HdlOption, also implement conversions <-> Option

#71 by programmerjake was merged 2026-05-02 01:55:41 +00:00

master

add support for custom debug/display formatting of #[hdl] structs/enums

#70 by programmerjake was merged 2026-05-01 06:18:30 +00:00

master

sim: Speed up updating traces by tracking which traces are written to

#69 by programmerjake was merged 2026-05-01 02:18:39 +00:00

master

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

#68 by programmerjake was merged 2026-03-27 02:19:16 +00:00

master

sim/compiler: fix registers so they properly retain their old value when not written

#67 by programmerjake was merged 2026-03-25 06:43:44 +00:00

master

make sure rust-src is always available and update ui test's expected output to match

#66 by programmerjake was merged 2026-03-18 03:54:42 +00:00

master

change VCD id generation to be based on hashing the path, making them better for git diff

#65 by programmerjake was merged 2026-02-24 04:18:26 +00:00

master

Run Rocq tests.

2

#64 by cesar was merged 2026-03-31 00:22:46 +00:00

master

1 approval

speed up simulation by optimizing SimulationImpl::read_traces

#63 by programmerjake was merged 2026-02-04 23:47:09 +00:00

master

speed up LazyInterned

#62 by programmerjake was merged 2026-02-04 02:11:57 +00:00

master

speed up interning

#61 by programmerjake was merged 2026-02-03 01:58:52 +00:00

master

don't compare function pointers -- they're non-deterministic

#60 by programmerjake was merged 2026-01-12 11:19:58 +00:00

master

Formally define design safety, and prove it for 1-step and 2-step induction

2

#59 by cesar was merged 2025-12-24 20:09:11 +00:00

master

1 approval

simplify SimValue Debug format, making complex structures much easier to read

#58 by programmerjake was merged 2025-12-15 05:03:58 +00:00

master

add FillInDefaultedGenerics<Type = Self> bound for SizeType

#57 by programmerjake was merged 2025-12-11 04:27:55 +00:00

master

Initial work on representing HDL and formal verification in Rocq.

1

#56 by cesar was merged 2025-12-09 16:34:36 +00:00

master

support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those

#55 by programmerjake was merged 2025-11-24 08:22:49 +00:00

master

support Rust's default binding modes when destructuring with #[hdl(sim)] let/match

#54 by programmerjake was merged 2025-11-14 08:27:17 +00:00

master