Labels Milestones

New pull request

0 Open 13 Closed

Label

Show archived labels

Use alt + click/enter to exclude labels

All labels No label

Milestone

All milestones No milestones

Project

All projects No project

Author

All authors

Assignee

All assignees No assignee

cesar postmaster programmerjake

Sort

Newest Oldest Recently updated Least recently updated Most commented Least commented Nearest due date Farthest due date

0 Open 13 Closed

Close

Label

Clear labels

Milestone

No milestone

Projects

Clear projects

Assignee

Clear assignees

No assignee

cesar

postmaster

programmerjake

sim: fix "label address not set" bug when the last Assignment is conditional

#16 by programmerjake was merged 2025-01-16 03:12:04 +00:00

master

programmerjake:fix_label_address_not_set_bug

tests/sim: add test_array_rw

#15 by programmerjake was merged 2025-01-13 06:02:20 +00:00

master

programmerjake:tests_sim_add_test_array_rw

properly handle duplicate names in vcd

#14 by programmerjake was merged 2025-01-10 07:11:44 +00:00

master

programmerjake:vcd-handle-duplicate-names

fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s

#13 by programmerjake was merged 2024-12-29 09:06:59 +00:00

master

programmerjake:fix-attr-span

implementing handling #[cfg] and #[cfg_attr] in proc macro inputs

#12 by programmerjake was merged 2024-12-29 07:50:06 +00:00

master

programmerjake:process-cfgs

Queue formal proof based on one-entry FIFO equivalence

3

#11 by cesar was merged 2024-12-29 21:05:26 +00:00

master

cesar:fifo-proof

1 change request

make sim::Compiler not print things to stdout unless you ask for it

#10 by programmerjake was merged 2024-12-19 05:28:51 +00:00

master

programmerjake:make_sim_stdout_less_verbose

sim: fix sim.write to struct

#9 by programmerjake was merged 2024-12-19 05:04:18 +00:00

master

programmerjake:fix-sim-write-struct

sim: add SimValue and reading/writing more than just a scalar

#8 by programmerjake was merged 2024-12-18 10:03:36 +00:00

master

adding-simulator

Add module exercising formal verification of memories

#7 by cesar was merged 2024-12-08 21:25:32 +00:00

master

cesar:formal_memories

Fix SInt::for_value not accounting for sign bit for positive values

#5 by programmerjake was merged 2024-11-27 00:38:37 +00:00

master

fix-sint-for_value

add a simulator

2

#3 by programmerjake was merged 2024-12-16 04:06:48 +00:00

master

adding-simulator

Add test module exercising formal verification.

1

#2 by cesar was merged 2024-11-20 21:40:35 +00:00

master

cesar:formal_test_case