sim: simple memory test works!
This commit is contained in:
parent
8d030ac65d
commit
903ca1bf30
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@ -519,7 +519,12 @@ impl<Element: Type, Len: Size> fmt::Debug for Mem<Element, Len> {
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f.debug_struct("Mem")
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.field("name", scoped_name)
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.field("array_type", array_type)
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.field("initial_value", initial_value)
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.field(
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"initial_value",
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&initial_value.as_ref().map(|initial_value| {
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DebugMemoryData::from_bit_slice(*array_type, initial_value)
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}),
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)
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.field("read_latency", read_latency)
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.field("write_latency", write_latency)
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.field("read_under_write", read_under_write)
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@ -1079,3 +1084,61 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
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)),
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}
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}
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pub trait DebugMemoryDataGetElement {
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fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice;
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}
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impl<'a, F: ?Sized + Fn(usize, Array) -> &'a BitSlice> DebugMemoryDataGetElement for &'a F {
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fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
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self(element_index, array_type)
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}
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}
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#[derive(Clone)]
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pub struct DebugMemoryData<GetElement: DebugMemoryDataGetElement> {
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pub array_type: Array,
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pub get_element: GetElement,
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}
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impl DebugMemoryDataGetElement for &'_ BitSlice {
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fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
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assert!(element_index < array_type.len());
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let stride = array_type.element().bit_width();
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let start = element_index
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.checked_mul(stride)
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.expect("memory is too big");
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let end = start.checked_add(stride).expect("memory is too big");
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&self[start..end]
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}
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}
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impl<'a> DebugMemoryData<&'a BitSlice> {
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pub fn from_bit_slice<T: Type, Depth: Size>(
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array_type: ArrayType<T, Depth>,
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bit_slice: &'a BitSlice,
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) -> Self {
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let array_type = array_type.as_dyn_array();
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assert_eq!(bit_slice.len(), array_type.type_properties().bit_width);
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Self {
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array_type,
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get_element: bit_slice,
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}
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}
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}
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impl<GetElement: DebugMemoryDataGetElement> fmt::Debug for DebugMemoryData<GetElement> {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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if self.array_type.len() == 0 {
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return f.write_str("[]");
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}
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writeln!(f, "[\n // len = {:#x}", self.array_type.len())?;
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for element_index in 0..self.array_type.len() {
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let element = crate::util::BitSliceWriteWithBase(
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self.get_element.get_element(element_index, self.array_type),
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);
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writeln!(f, " [{element_index:#x}]: {element:#x},")?;
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}
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f.write_str("]")
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}
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}
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@ -26,12 +26,13 @@ use crate::{
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reset::{ResetType, ResetTypeDispatch},
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sim::{
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interpreter::{
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Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding,
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InsnsBuildingDone, InsnsBuildingKind, Label, SlotDebugData, SmallUInt, State,
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StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex, StatePartIndexRange,
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StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots,
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StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
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TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
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BreakAction, BreakpointsSet, Insn, InsnField, InsnFieldKind, InsnFieldType,
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InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label,
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MemoryData, RunResult, SlotDebugData, SmallUInt, State, StatePartArrayIndex,
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StatePartArrayIndexed, StatePartIndex, StatePartIndexRange, StatePartKind,
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StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout,
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StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex,
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TypeIndexRange, TypeLayout, TypeLen, TypeParts,
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},
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time::{SimDuration, SimInstant},
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},
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@ -4274,12 +4275,15 @@ impl Compiler {
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.memories
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.allocate(&StatePartLayout::scalar(
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(),
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mem.initial_value().unwrap_or_else(|| {
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Intern::intern_owned(BitVec::repeat(
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false,
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mem.array_type().type_properties().bit_width,
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))
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}),
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MemoryData {
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array_type: mem.array_type(),
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data: mem.initial_value().unwrap_or_else(|| {
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Intern::intern_owned(BitVec::repeat(
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false,
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mem.array_type().type_properties().bit_width,
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))
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}),
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},
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))
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.start;
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let (ports, trace_ports) = mem
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@ -4765,9 +4769,10 @@ impl Compiler {
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source_location,
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}| {
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self.insns.push(
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Insn::NotSmall {
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Insn::XorSmallImmediate {
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dest: last_clk_was_low,
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src: clk,
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lhs: clk,
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rhs: 1,
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},
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source_location,
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);
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@ -4857,14 +4862,6 @@ impl Compiler {
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} in mem::take(ports)
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{
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let port_end = self.insns.new_label();
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self.insns.push(
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Insn::BranchIfSmallZero {
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target: port_end.0,
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value: clk_triggered,
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},
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mem.source_location(),
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);
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self.insns.extend(write_insns, mem.source_location());
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let small_shift_reg =
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|this: &mut Self, values: &[StatePartIndex<StatePartKindSmallSlots>]| {
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for pair in values.windows(2).rev() {
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@ -4883,12 +4880,20 @@ impl Compiler {
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.extend(pair[0].insns_for_copy_to(pair[1]), mem.source_location());
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}
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};
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self.insns.push(
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Insn::BranchIfSmallZero {
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target: port_end.0,
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value: clk_triggered,
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},
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mem.source_location(),
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);
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small_shift_reg(self, &addr_delayed);
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small_shift_reg(self, &en_delayed);
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shift_reg(self, &read_data_delayed);
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shift_reg(self, &write_data_delayed);
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shift_reg(self, &write_mask_delayed);
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small_shift_reg(self, &write_mode_delayed);
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shift_reg(self, &read_data_delayed);
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self.insns.extend(write_insns, mem.source_location());
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self.insns.define_label_at_next_insn(port_end);
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}
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}
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@ -5814,9 +5819,50 @@ struct SimulationImpl {
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trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
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instant: SimInstant,
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clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
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breakpoints: Option<BreakpointsSet>,
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}
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impl fmt::Debug for SimulationImpl {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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self.debug_fmt(None, f)
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}
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}
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impl SimulationImpl {
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fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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let Self {
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state,
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io: self_io,
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uninitialized_inputs,
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io_targets,
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made_initial_step,
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needs_settle,
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trace_decls,
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traces,
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trace_memories,
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trace_writers,
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instant,
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clocks_triggered,
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breakpoints: _,
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} = self;
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f.debug_struct("Simulation")
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.field("state", state)
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.field("io", io.unwrap_or(self_io))
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.field(
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"uninitialized_inputs",
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&SortedSetDebug(uninitialized_inputs),
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)
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.field("io_targets", &SortedMapDebug(io_targets))
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.field("made_initial_step", made_initial_step)
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.field("needs_settle", needs_settle)
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.field("trace_decls", trace_decls)
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.field("traces", traces)
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.field("trace_memories", trace_memories)
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.field("trace_writers", trace_writers)
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.field("instant", instant)
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.field("clocks_triggered", clocks_triggered)
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.finish_non_exhaustive()
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}
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fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) {
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self.io_targets.insert(target, value);
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match value.layout.body {
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@ -5876,6 +5922,7 @@ impl SimulationImpl {
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trace_writers: vec![],
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instant: SimInstant::START,
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clocks_triggered: compiled.clocks_triggered,
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breakpoints: None,
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};
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let io_target = Target::from(compiled.io);
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for (BundleField { name, .. }, value) in compiled
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@ -5905,7 +5952,7 @@ impl SimulationImpl {
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trace_writer.set_memory_element(
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self.trace_memories[&memory].id,
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element_index,
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&self.state.memories[memory][start..end],
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&self.state.memories[memory].data[start..end],
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)
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};
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if ONLY_IF_CHANGED {
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@ -6054,7 +6101,30 @@ impl SimulationImpl {
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return;
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}
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self.state.setup_call(0);
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self.state.run();
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if self.breakpoints.is_some() {
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loop {
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match self
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.state
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.run(self.breakpoints.as_mut().expect("just checked"))
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{
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RunResult::Break(break_action) => {
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println!(
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"hit breakpoint at:\n{:?}",
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self.state.debug_insn_at(self.state.pc),
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);
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match break_action {
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BreakAction::DumpStateAndContinue => {
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println!("{self:#?}");
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}
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BreakAction::Continue => {}
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}
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}
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RunResult::Return(()) => break,
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}
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}
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} else {
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let RunResult::Return(()) = self.state.run(());
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}
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if self.made_initial_step {
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self.read_traces::<false>();
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} else {
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@ -6097,7 +6167,7 @@ impl SimulationImpl {
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if Some(&target) == self.io.target().as_deref()
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|| Some(target.base()) != self.io.target().map(|v| v.base())
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{
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panic!("simulator read/write expression must be an array element/field of `Simulator::io()`");
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panic!("simulator read/write expression must be an array element/field of `Simulation::io()`");
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};
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panic!("simulator read/write expression must not have dynamic array indexes");
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}
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@ -6361,41 +6431,8 @@ impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
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impl<T: BundleType> fmt::Debug for Simulation<T> {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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let Self {
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sim_impl:
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SimulationImpl {
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state,
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io: _,
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uninitialized_inputs,
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io_targets,
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made_initial_step,
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needs_settle,
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trace_decls,
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traces,
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trace_memories,
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trace_writers,
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instant,
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clocks_triggered,
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},
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io,
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} = self;
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f.debug_struct("Simulation")
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.field("state", state)
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.field("io", io)
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.field(
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"uninitialized_inputs",
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&SortedSetDebug(uninitialized_inputs),
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)
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.field("io_targets", &SortedMapDebug(io_targets))
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.field("made_initial_step", made_initial_step)
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.field("needs_settle", needs_settle)
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.field("trace_decls", trace_decls)
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.field("traces", traces)
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.field("trace_memories", trace_memories)
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.field("trace_writers", trace_writers)
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.field("instant", instant)
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.field("clocks_triggered", clocks_triggered)
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.finish()
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let Self { sim_impl, io } = self;
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sim_impl.debug_fmt(Some(io), f)
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}
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}
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@ -6488,4 +6525,13 @@ impl<T: BundleType> Simulation<T> {
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pub fn read_reset<R: ResetType>(&mut self, io: Expr<R>) -> bool {
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self.sim_impl.read_bit(Expr::canonical(io))
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}
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#[doc(hidden)]
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/// This is explicitly unstable and may be changed/removed at any time
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pub fn set_breakpoints_unstable(&mut self, pcs: HashSet<usize>, trace: bool) {
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self.sim_impl.breakpoints = Some(BreakpointsSet {
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last_was_break: false,
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set: pcs,
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trace,
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});
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}
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}
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@ -2,6 +2,7 @@
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// See Notices.txt for copyright information
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use crate::{
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array::Array,
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int::{BoolOrIntType, SInt, UInt},
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intern::{Intern, Interned, Memoize},
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source_location::SourceLocation,
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@ -9,17 +10,17 @@ use crate::{
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util::get_many_mut,
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};
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use bitvec::{boxed::BitBox, slice::BitSlice};
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use hashbrown::HashMap;
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use hashbrown::{HashMap, HashSet};
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use num_bigint::BigInt;
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use num_traits::{One, Signed, ToPrimitive, Zero};
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use std::{
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any::TypeId,
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borrow::BorrowMut,
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convert::Infallible,
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fmt,
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fmt::{self, Write},
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hash::{Hash, Hasher},
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marker::PhantomData,
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ops::{Deref, DerefMut, Index, IndexMut},
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ops::{ControlFlow, Deref, DerefMut, Index, IndexMut},
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};
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use vec_map::VecMap;
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@ -174,7 +175,37 @@ fn make_array_into_iter<T, const I: usize, const N: usize>(
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impl fmt::Debug for Insn {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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self.debug_fmt::<InsnsBuildingDone>(f, None, None)
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self.debug_fmt::<InsnsBuildingDone>(f, None, None, None)
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}
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}
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struct PrefixLinesWrapper<'a, W> {
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writer: W,
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at_beginning_of_line: bool,
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blank_line_prefix: &'a str,
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line_prefix: &'a str,
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}
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impl<T: fmt::Write> fmt::Write for PrefixLinesWrapper<'_, T> {
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fn write_str(&mut self, input: &str) -> fmt::Result {
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for part in input.split_inclusive('\n') {
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if part.is_empty() {
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continue;
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}
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if self.at_beginning_of_line {
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let prefix = match part {
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"\n" => self.blank_line_prefix,
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_ => self.line_prefix,
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};
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if !prefix.is_empty() {
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self.writer.write_str(prefix)?;
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}
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self.at_beginning_of_line = false;
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}
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self.writer.write_str(part)?;
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self.at_beginning_of_line = part.ends_with('\n');
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}
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Ok(())
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}
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}
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@ -184,15 +215,22 @@ impl Insn {
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f: &mut fmt::Formatter<'_>,
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labels: Option<&Labels>,
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state_layout: Option<&StateLayout<BK>>,
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state: Option<&State>,
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) -> fmt::Result {
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let (insn_name, fields) = self.fields_with_names();
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write!(f, "{insn_name}")?;
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if fields.len() == 0 {
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return Ok(());
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}
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let mut f = PrefixLinesWrapper {
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writer: f,
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at_beginning_of_line: false,
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blank_line_prefix: "",
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line_prefix: " ",
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};
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writeln!(f, " {{")?;
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for (field_name, field) in fields {
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write!(f, " {field_name}: ")?;
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write!(f, "{field_name}: ")?;
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match field.kind {
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InsnFieldKind::BranchTarget => match field.ty {
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InsnFieldType::USize(&label_index) => {
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|
@ -227,35 +265,100 @@ impl Insn {
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| InsnFieldKind::Output
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| InsnFieldKind::Immediate => {}
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}
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macro_rules! debug_fmt_state_part {
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($v:expr) => {
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$v.debug_fmt(&mut f, ",", " // ", " // ", "", state_layout, state)
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};
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}
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match field.ty {
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InsnFieldType::Memory(v) => {
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v.debug_fmt(f, ",", " // ", "", state_layout)?;
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debug_fmt_state_part!(v)?;
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}
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InsnFieldType::SmallSlot(v) => {
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v.debug_fmt(f, ",", " // ", "", state_layout)?;
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debug_fmt_state_part!(v)?;
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}
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InsnFieldType::BigSlot(v) => {
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v.debug_fmt(f, ",", " // ", "", state_layout)?;
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debug_fmt_state_part!(v)?;
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}
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InsnFieldType::SmallSlotArrayIndexed(v) => {
|
||||
v.debug_fmt(f, ",", " // ", "", state_layout)?;
|
||||
debug_fmt_state_part!(v)?;
|
||||
}
|
||||
InsnFieldType::BigSlotArrayIndexed(v) => {
|
||||
v.debug_fmt(f, ",", " // ", "", state_layout)?;
|
||||
debug_fmt_state_part!(v)?;
|
||||
}
|
||||
InsnFieldType::SmallUInt(v) => fmt::Debug::fmt(v, f)?,
|
||||
InsnFieldType::SmallSInt(v) => fmt::Debug::fmt(v, f)?,
|
||||
InsnFieldType::InternedBigInt(v) => fmt::Debug::fmt(v, f)?,
|
||||
InsnFieldType::U8(v) => fmt::Debug::fmt(v, f)?,
|
||||
InsnFieldType::USize(v) => fmt::Debug::fmt(v, f)?,
|
||||
InsnFieldType::Empty(v) => fmt::Debug::fmt(v, f)?,
|
||||
InsnFieldType::SmallUInt(v) => write!(f, "{v:#x}")?,
|
||||
InsnFieldType::SmallSInt(v) => write!(f, "{v:#x}")?,
|
||||
InsnFieldType::InternedBigInt(v) => write!(f, "{v:#x}")?,
|
||||
InsnFieldType::U8(v) => write!(f, "{v:#x}")?,
|
||||
InsnFieldType::USize(v) => write!(f, "{v}")?,
|
||||
InsnFieldType::Empty(v) => write!(f, "{v:?}")?,
|
||||
}
|
||||
writeln!(f, ",")?;
|
||||
}
|
||||
write!(f, "}}")
|
||||
write!(f.writer, "}}")
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) trait Breakpoints {
|
||||
type Break;
|
||||
fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break>;
|
||||
}
|
||||
|
||||
impl<T: ?Sized + Breakpoints> Breakpoints for &'_ mut T {
|
||||
type Break = T::Break;
|
||||
fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
|
||||
T::check_for_breakpoint(self, pc)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: ?Sized + Breakpoints> Breakpoints for Box<T> {
|
||||
type Break = T::Break;
|
||||
fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
|
||||
T::check_for_breakpoint(self, pc)
|
||||
}
|
||||
}
|
||||
|
||||
impl Breakpoints for () {
|
||||
type Break = Infallible;
|
||||
fn check_for_breakpoint(&mut self, _pc: usize) -> ControlFlow<Self::Break> {
|
||||
ControlFlow::Continue(())
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) struct BreakpointsSet {
|
||||
pub(crate) last_was_break: bool,
|
||||
pub(crate) set: HashSet<usize>,
|
||||
pub(crate) trace: bool,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
|
||||
pub(crate) enum BreakAction {
|
||||
DumpStateAndContinue,
|
||||
Continue,
|
||||
}
|
||||
|
||||
impl Breakpoints for BreakpointsSet {
|
||||
type Break = BreakAction;
|
||||
fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
|
||||
let retval = if self.last_was_break {
|
||||
ControlFlow::Continue(())
|
||||
} else if self.set.contains(&pc) {
|
||||
ControlFlow::Break(BreakAction::DumpStateAndContinue)
|
||||
} else if self.trace {
|
||||
ControlFlow::Break(BreakAction::Continue)
|
||||
} else {
|
||||
ControlFlow::Continue(())
|
||||
};
|
||||
self.last_was_break = retval.is_break();
|
||||
retval
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) enum RunResult<Break, Return> {
|
||||
Break(Break),
|
||||
Return(Return),
|
||||
}
|
||||
|
||||
macro_rules! impl_insns {
|
||||
(
|
||||
#[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
|
||||
|
@ -402,11 +505,14 @@ macro_rules! impl_insns {
|
|||
}
|
||||
|
||||
impl $State {
|
||||
$vis fn $run(&mut $self) -> $run_ret_ty {
|
||||
$vis fn $run<B: Breakpoints>(&mut $self, mut breakpoints: B) -> RunResult<B::Break, $run_ret_ty> {
|
||||
let mut $state = $state_init;
|
||||
$($setup)*
|
||||
let mut insn = $state.insns[$state.pc];
|
||||
let retval = 'main_loop: loop {
|
||||
if let ControlFlow::Break(b) = breakpoints.check_for_breakpoint($state.pc) {
|
||||
break RunResult::Break(b);
|
||||
}
|
||||
macro_rules! $next_macro {
|
||||
() => {
|
||||
$state.pc += 1;
|
||||
|
@ -542,6 +648,7 @@ struct InsnsDebug<'a, BK: InsnsBuildingKind> {
|
|||
insn_source_locations: &'a [SourceLocation],
|
||||
labels: &'a BK::Labels,
|
||||
state_layout: &'a StateLayout<BK>,
|
||||
state: Option<&'a State>,
|
||||
}
|
||||
|
||||
struct InsnDebug<'a, BK: InsnsBuildingKind> {
|
||||
|
@ -550,6 +657,7 @@ struct InsnDebug<'a, BK: InsnsBuildingKind> {
|
|||
insn: &'a Insn,
|
||||
labels: Option<&'a Labels>,
|
||||
state_layout: &'a StateLayout<BK>,
|
||||
state: Option<&'a State>,
|
||||
}
|
||||
|
||||
impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
|
||||
|
@ -566,7 +674,8 @@ impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
|
|||
writeln!(f, "// at: {source_location}")?;
|
||||
}
|
||||
write!(f, "{}: ", self.address)?;
|
||||
self.insn.debug_fmt(f, self.labels, Some(self.state_layout))
|
||||
self.insn
|
||||
.debug_fmt(f, self.labels, Some(self.state_layout), self.state)
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -591,6 +700,7 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
|
|||
insn,
|
||||
labels,
|
||||
state_layout: self.state_layout,
|
||||
state: self.state,
|
||||
});
|
||||
last_source_location = Some(source_location);
|
||||
}
|
||||
|
@ -598,8 +708,45 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
|
|||
}
|
||||
}
|
||||
|
||||
impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
|
||||
impl<BK: InsnsBuildingKind> Insns<BK> {
|
||||
pub(crate) fn debug_insn_at<'a>(
|
||||
&'a self,
|
||||
address: usize,
|
||||
state: Option<&'a State>,
|
||||
) -> impl fmt::Debug + 'a {
|
||||
let Self {
|
||||
insns,
|
||||
insn_source_locations,
|
||||
labels,
|
||||
state_layout,
|
||||
} = self;
|
||||
InsnDebug {
|
||||
address,
|
||||
source_location: Some(insn_source_locations[address]),
|
||||
insn: &insns[address],
|
||||
labels: BK::labels(labels),
|
||||
state_layout,
|
||||
state,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl State {
|
||||
pub(crate) fn debug_insn_at(&self, address: usize) -> impl fmt::Debug + '_ {
|
||||
self.insns.debug_insn_at(address, Some(self))
|
||||
}
|
||||
}
|
||||
|
||||
struct InsnsOfState<'a>(&'a State);
|
||||
|
||||
impl fmt::Debug for InsnsOfState<'_> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
self.0.insns.debug_fmt(Some(self.0), f)
|
||||
}
|
||||
}
|
||||
|
||||
impl<BK: InsnsBuildingKind> Insns<BK> {
|
||||
fn debug_fmt(&self, state: Option<&State>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let Self {
|
||||
insns,
|
||||
insn_source_locations,
|
||||
|
@ -615,12 +762,19 @@ impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
|
|||
insn_source_locations,
|
||||
labels,
|
||||
state_layout,
|
||||
state,
|
||||
},
|
||||
)
|
||||
.finish_non_exhaustive()
|
||||
}
|
||||
}
|
||||
|
||||
impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
self.debug_fmt(None, f)
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) trait StatePartKind:
|
||||
Send + Sync + Ord + Hash + fmt::Debug + 'static + Copy + Default
|
||||
{
|
||||
|
@ -635,6 +789,11 @@ pub(crate) trait StatePartKind:
|
|||
state_layout: &StateLayout<BK>,
|
||||
part_index: StatePartIndex<Self>,
|
||||
) -> Option<&Self::DebugData>;
|
||||
fn debug_fmt_state_value(
|
||||
state: &State,
|
||||
index: StatePartIndex<Self>,
|
||||
f: &mut impl fmt::Write,
|
||||
) -> fmt::Result;
|
||||
}
|
||||
|
||||
pub(crate) trait StatePartsValue {
|
||||
|
@ -987,7 +1146,6 @@ macro_rules! make_state_part_kinds {
|
|||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub(crate) struct State {
|
||||
pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
|
||||
pub(crate) pc: usize,
|
||||
|
@ -996,6 +1154,25 @@ macro_rules! make_state_part_kinds {
|
|||
$(pub(crate) $type_field: StatePart<$TypeKind>,)*
|
||||
}
|
||||
|
||||
impl fmt::Debug for State {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let Self {
|
||||
insns: _,
|
||||
pc,
|
||||
memory_write_log,
|
||||
$($state_field,)*
|
||||
$($type_field,)*
|
||||
} = self;
|
||||
f.debug_struct("State")
|
||||
.field("insns", &InsnsOfState(self))
|
||||
.field("pc", pc)
|
||||
.field("memory_write_log", memory_write_log)
|
||||
$(.field(stringify!($state_field), $state_field))*
|
||||
$(.field(stringify!($type_field), $type_field))*
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
|
||||
impl State {
|
||||
pub(crate) fn new(insns: Interned<Insns<InsnsBuildingDone>>) -> Self {
|
||||
Self {
|
||||
|
@ -1199,6 +1376,25 @@ macro_rules! make_state_part_kinds {
|
|||
};
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, Hash, PartialEq, Eq)]
|
||||
pub(crate) struct MemoryData<T: Deref<Target = BitSlice>> {
|
||||
pub(crate) array_type: Array,
|
||||
pub(crate) data: T,
|
||||
}
|
||||
|
||||
impl<T: Deref<Target = BitSlice>> fmt::Debug for MemoryData<T> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let Self { array_type, data } = self;
|
||||
f.debug_struct("MemoryData")
|
||||
.field("array_type", array_type)
|
||||
.field(
|
||||
"data",
|
||||
&crate::memory::DebugMemoryData::from_bit_slice(*array_type, data),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
|
||||
make_state_part_kinds! {
|
||||
/*#[state, field = small_stack]
|
||||
impl StatePartKind for StatePartKindSmallStack {
|
||||
|
@ -1244,11 +1440,14 @@ make_state_part_kinds! {
|
|||
impl StatePartKind for StatePartKindMemories {
|
||||
const NAME: &'static str = "Memories";
|
||||
type DebugData = ();
|
||||
type LayoutData = Interned<BitSlice>;
|
||||
type State = Box<[BitBox]>;
|
||||
type BorrowedState<'a> = &'a mut [BitBox];
|
||||
type LayoutData = MemoryData<Interned<BitSlice>>;
|
||||
type State = Box<[MemoryData<BitBox>]>;
|
||||
type BorrowedState<'a> = &'a mut [MemoryData<BitBox>];
|
||||
fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
|
||||
layout_data.iter().map(|initial_data| BitBox::from_bitslice(initial_data)).collect()
|
||||
layout_data.iter().map(|MemoryData { array_type, data }| MemoryData {
|
||||
array_type: *array_type,
|
||||
data: BitBox::from_bitslice(data),
|
||||
}).collect()
|
||||
}
|
||||
fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
|
||||
state
|
||||
|
@ -1259,6 +1458,13 @@ make_state_part_kinds! {
|
|||
) -> Option<&Self::DebugData> {
|
||||
state_layout.memories.debug_data.get(part_index.as_usize())
|
||||
}
|
||||
fn debug_fmt_state_value(
|
||||
state: &State,
|
||||
index: StatePartIndex<Self>,
|
||||
f: &mut impl fmt::Write,
|
||||
) -> fmt::Result {
|
||||
write!(f, "{:#?}", &state.memories[index])
|
||||
}
|
||||
}
|
||||
#[type, field = small_slots]
|
||||
impl StatePartKind for StatePartKindSmallSlots {
|
||||
|
@ -1279,6 +1485,15 @@ make_state_part_kinds! {
|
|||
) -> Option<&Self::DebugData> {
|
||||
state_layout.ty.small_slots.debug_data.get(part_index.as_usize())
|
||||
}
|
||||
fn debug_fmt_state_value(
|
||||
state: &State,
|
||||
index: StatePartIndex<Self>,
|
||||
f: &mut impl fmt::Write,
|
||||
) -> fmt::Result {
|
||||
let value = state.small_slots[index];
|
||||
write!(f, "{value:#x} {}", value as SmallSInt)?;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
#[type, field = big_slots]
|
||||
impl StatePartKind for StatePartKindBigSlots {
|
||||
|
@ -1299,6 +1514,13 @@ make_state_part_kinds! {
|
|||
) -> Option<&Self::DebugData> {
|
||||
state_layout.ty.big_slots.debug_data.get(part_index.as_usize())
|
||||
}
|
||||
fn debug_fmt_state_value(
|
||||
state: &State,
|
||||
index: StatePartIndex<Self>,
|
||||
f: &mut impl fmt::Write,
|
||||
) -> fmt::Result {
|
||||
write!(f, "{:#x}", state.big_slots[index])
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1474,37 +1696,32 @@ pub(crate) struct StatePartArrayIndexed<K: StatePartKind> {
|
|||
impl<K: StatePartKind> StatePartArrayIndexed<K> {
|
||||
pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
|
||||
&self,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
f: &mut impl fmt::Write,
|
||||
before_debug_info_text: &str,
|
||||
comment_start: &str,
|
||||
comment_line_start: &str,
|
||||
comment_end: &str,
|
||||
state_layout: Option<&StateLayout<BK>>,
|
||||
state: Option<&State>,
|
||||
) -> fmt::Result {
|
||||
if let Some(state_layout) = state_layout {
|
||||
let Self { base, indexes } = *self;
|
||||
if indexes.is_empty() {
|
||||
base.debug_fmt(
|
||||
f,
|
||||
before_debug_info_text,
|
||||
comment_start,
|
||||
comment_end,
|
||||
Some(state_layout),
|
||||
)
|
||||
} else {
|
||||
base.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
|
||||
for StatePartArrayIndex { index, len, stride } in indexes {
|
||||
f.write_str("[")?;
|
||||
index.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
|
||||
write!(f, ", len={len}, stride={}]", stride.value)?;
|
||||
}
|
||||
f.write_str(before_debug_info_text)
|
||||
}
|
||||
let Self { base, indexes } = *self;
|
||||
if indexes.is_empty() {
|
||||
base.debug_fmt(
|
||||
f,
|
||||
before_debug_info_text,
|
||||
comment_start,
|
||||
comment_line_start,
|
||||
comment_end,
|
||||
state_layout,
|
||||
state,
|
||||
)
|
||||
} else {
|
||||
let Self { base, indexes } = self;
|
||||
f.debug_struct("StatePartArrayIndexed")
|
||||
.field("base", base)
|
||||
.field("indexes", indexes)
|
||||
.finish()?;
|
||||
base.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
|
||||
for StatePartArrayIndex { index, len, stride } in indexes {
|
||||
f.write_str("[")?;
|
||||
index.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
|
||||
write!(f, ", len={len}, stride={}]", stride.value)?;
|
||||
}
|
||||
f.write_str(before_debug_info_text)
|
||||
}
|
||||
}
|
||||
|
@ -1512,7 +1729,7 @@ impl<K: StatePartKind> StatePartArrayIndexed<K> {
|
|||
|
||||
impl<K: StatePartKind + fmt::Debug> fmt::Debug for StatePartArrayIndexed<K> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
|
||||
self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1579,18 +1796,40 @@ impl<K: StatePartKind> StatePartIndex<K> {
|
|||
}
|
||||
pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
|
||||
&self,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
f: &mut impl fmt::Write,
|
||||
before_debug_info_text: &str,
|
||||
comment_start: &str,
|
||||
comment_line_start: &str,
|
||||
comment_end: &str,
|
||||
state_layout: Option<&StateLayout<BK>>,
|
||||
state: Option<&State>,
|
||||
) -> fmt::Result {
|
||||
write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)?;
|
||||
f.write_str(before_debug_info_text)?;
|
||||
if let Some(state_layout) = state_layout {
|
||||
if let Some(debug_data) = K::part_debug_data(state_layout, *self) {
|
||||
write!(f, "{comment_start}{debug_data:?}{comment_end}")?;
|
||||
}
|
||||
let debug_data =
|
||||
state_layout.and_then(|state_layout| K::part_debug_data(state_layout, *self));
|
||||
if state.is_some() || debug_data.is_some() {
|
||||
f.write_str(comment_start)?;
|
||||
}
|
||||
let mut f = PrefixLinesWrapper {
|
||||
writer: f,
|
||||
at_beginning_of_line: false,
|
||||
blank_line_prefix: comment_line_start.trim_end(),
|
||||
line_prefix: comment_line_start,
|
||||
};
|
||||
if let Some(state) = state {
|
||||
f.write_str("(")?;
|
||||
K::debug_fmt_state_value(state, *self, &mut f)?;
|
||||
f.write_str(")")?;
|
||||
}
|
||||
if state.is_some() && debug_data.is_some() {
|
||||
f.write_str(" ")?;
|
||||
}
|
||||
if let Some(debug_data) = debug_data {
|
||||
write!(f, "{debug_data:?}")?;
|
||||
}
|
||||
if state.is_some() || debug_data.is_some() {
|
||||
f.writer.write_str(comment_end)?;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
@ -1598,7 +1837,7 @@ impl<K: StatePartKind> StatePartIndex<K> {
|
|||
|
||||
impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
|
||||
self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -2182,7 +2421,7 @@ impl BorrowedState<'_> {
|
|||
let Ok(addr) = usize::try_from(addr) else {
|
||||
return;
|
||||
};
|
||||
if addr < self.memories.value.len() {
|
||||
if addr < self.memories[memory].array_type.len() {
|
||||
let log_entry = (memory, addr);
|
||||
if self.memory_write_log.last().copied() == Some(log_entry) {
|
||||
return;
|
||||
|
@ -2521,6 +2760,18 @@ impl_insns! {
|
|||
state.big_slots[dest] = value;
|
||||
next!();
|
||||
}
|
||||
XorSmallImmediate {
|
||||
#[kind = Output]
|
||||
dest: StatePartIndex<StatePartKindSmallSlots>,
|
||||
#[kind = Input]
|
||||
lhs: StatePartIndex<StatePartKindSmallSlots>,
|
||||
#[kind = Immediate]
|
||||
rhs: SmallUInt,
|
||||
} => {
|
||||
let value = state.small_slots[lhs] ^ rhs;
|
||||
state.small_slots[dest] = value;
|
||||
next!();
|
||||
}
|
||||
NotS {
|
||||
#[kind = Output]
|
||||
dest: StatePartIndex<StatePartKindBigSlots>,
|
||||
|
@ -2543,16 +2794,6 @@ impl_insns! {
|
|||
state.big_slots[dest] = value;
|
||||
next!();
|
||||
}
|
||||
NotSmall {
|
||||
#[kind = Output]
|
||||
dest: StatePartIndex<StatePartKindSmallSlots>,
|
||||
#[kind = Input]
|
||||
src: StatePartIndex<StatePartKindSmallSlots>,
|
||||
} => {
|
||||
let value = !state.small_slots[src];
|
||||
state.small_slots[dest] = value;
|
||||
next!();
|
||||
}
|
||||
Neg {
|
||||
#[kind = Output]
|
||||
dest: StatePartIndex<StatePartKindBigSlots>,
|
||||
|
@ -2879,7 +3120,7 @@ impl_insns! {
|
|||
width: usize,
|
||||
} => {
|
||||
let addr = state.small_slots[addr];
|
||||
state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
|
||||
state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
|
||||
next!();
|
||||
}
|
||||
MemoryReadSInt {
|
||||
|
@ -2897,7 +3138,7 @@ impl_insns! {
|
|||
width: usize,
|
||||
} => {
|
||||
let addr = state.small_slots[addr];
|
||||
state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
|
||||
state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
|
||||
next!();
|
||||
}
|
||||
MemoryWriteUInt {
|
||||
|
@ -2915,7 +3156,7 @@ impl_insns! {
|
|||
width: usize,
|
||||
} => {
|
||||
let addr = state.small_slots[addr];
|
||||
memory_write_big::<UInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
|
||||
memory_write_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
|
||||
state.log_memory_write(memory, addr);
|
||||
next!();
|
||||
}
|
||||
|
@ -2934,11 +3175,11 @@ impl_insns! {
|
|||
width: usize,
|
||||
} => {
|
||||
let addr = state.small_slots[addr];
|
||||
memory_write_big::<SInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
|
||||
memory_write_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
|
||||
state.log_memory_write(memory, addr);
|
||||
next!();
|
||||
}
|
||||
Return => {
|
||||
break;
|
||||
break RunResult::Return(());
|
||||
}
|
||||
}
|
||||
|
|
|
@ -509,7 +509,6 @@ pub fn memories() {
|
|||
connect_any(mem.new_write_port(), w);
|
||||
}
|
||||
|
||||
#[cfg(todo)] // TODO: finish
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_memories() {
|
||||
|
@ -529,15 +528,107 @@ fn test_memories() {
|
|||
w_data: (u8, i8),
|
||||
w_mask: (bool, bool),
|
||||
}
|
||||
let io_cycles = [IO {
|
||||
r_addr: 0,
|
||||
r_en: false,
|
||||
r_data: (0, 0),
|
||||
w_addr: 0,
|
||||
w_en: false,
|
||||
w_data: (0, 0),
|
||||
w_mask: (false, false),
|
||||
}];
|
||||
let io_cycles = [
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: false,
|
||||
r_data: (0, 0),
|
||||
w_addr: 0,
|
||||
w_en: false,
|
||||
w_data: (0, 0),
|
||||
w_mask: (false, false),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x1, 0x23),
|
||||
w_addr: 0,
|
||||
w_en: true,
|
||||
w_data: (0x10, 0x20),
|
||||
w_mask: (true, true),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x10, 0x20),
|
||||
w_addr: 0,
|
||||
w_en: true,
|
||||
w_data: (0x30, 0x40),
|
||||
w_mask: (false, true),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x10, 0x40),
|
||||
w_addr: 0,
|
||||
w_en: true,
|
||||
w_data: (0x50, 0x60),
|
||||
w_mask: (true, false),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x50, 0x40),
|
||||
w_addr: 0,
|
||||
w_en: true,
|
||||
w_data: (0x70, -0x80),
|
||||
w_mask: (false, false),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x50, 0x40),
|
||||
w_addr: 0,
|
||||
w_en: false,
|
||||
w_data: (0x90, 0xA0u8 as i8),
|
||||
w_mask: (false, false),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x50, 0x40),
|
||||
w_addr: 1,
|
||||
w_en: true,
|
||||
w_data: (0x90, 0xA0u8 as i8),
|
||||
w_mask: (true, true),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x50, 0x40),
|
||||
w_addr: 2,
|
||||
w_en: true,
|
||||
w_data: (0xB0, 0xC0u8 as i8),
|
||||
w_mask: (true, true),
|
||||
},
|
||||
IO {
|
||||
r_addr: 0,
|
||||
r_en: true,
|
||||
r_data: (0x50, 0x40),
|
||||
w_addr: 2,
|
||||
w_en: false,
|
||||
w_data: (0xD0, 0xE0u8 as i8),
|
||||
w_mask: (true, true),
|
||||
},
|
||||
IO {
|
||||
r_addr: 1,
|
||||
r_en: true,
|
||||
r_data: (0x90, 0xA0u8 as i8),
|
||||
w_addr: 2,
|
||||
w_en: false,
|
||||
w_data: (0xD0, 0xE0u8 as i8),
|
||||
w_mask: (true, true),
|
||||
},
|
||||
IO {
|
||||
r_addr: 2,
|
||||
r_en: true,
|
||||
r_data: (0xB0, 0xC0u8 as i8),
|
||||
w_addr: 2,
|
||||
w_en: false,
|
||||
w_data: (0xD0, 0xE0u8 as i8),
|
||||
w_mask: (true, true),
|
||||
},
|
||||
];
|
||||
for (
|
||||
cycle,
|
||||
expected @ IO {
|
||||
|
|
|
@ -33,13 +33,13 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
0: Const {
|
||||
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
|
||||
value: 5,
|
||||
dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
|
||||
value: 0x5,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
1: Copy {
|
||||
dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
|
||||
dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
|
||||
src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
2: Return,
|
||||
|
@ -138,4 +138,5 @@ Simulation {
|
|||
trace_writers: [],
|
||||
instant: 0 s,
|
||||
clocks_triggered: [],
|
||||
..
|
||||
}
|
|
@ -45,27 +45,27 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
0: Const {
|
||||
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
value: 1,
|
||||
dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
value: 0x1,
|
||||
},
|
||||
1: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
|
||||
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
|
||||
src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
2: Copy {
|
||||
dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
|
||||
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
|
||||
dest: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
|
||||
src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
3: Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
|
||||
dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
4: Copy {
|
||||
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
5: Return,
|
||||
|
@ -225,4 +225,5 @@ Simulation {
|
|||
],
|
||||
instant: 1 μs,
|
||||
clocks_triggered: [],
|
||||
..
|
||||
}
|
|
@ -82,85 +82,86 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
0: Const {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
value: 1,
|
||||
dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
value: 0x1,
|
||||
},
|
||||
1: Copy {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
|
||||
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
2: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
|
||||
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
3: Const {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 3,
|
||||
dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 0x3,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
4: BranchIfZero {
|
||||
target: 6,
|
||||
value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
5: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
6: Add {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
|
||||
lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
7: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
|
||||
dest_width: 4,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
8: Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:6:1
|
||||
9: Copy {
|
||||
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
10: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
|
||||
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
|
||||
},
|
||||
11: AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
12: BranchIfSmallNonZero {
|
||||
target: 16,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
13: BranchIfSmallZero {
|
||||
target: 17,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
14: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
},
|
||||
15: Branch {
|
||||
target: 17,
|
||||
},
|
||||
16: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
17: NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
17: XorSmallImmediate {
|
||||
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: 0x1,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
18: Return,
|
||||
|
@ -174,7 +175,7 @@ Simulation {
|
|||
},
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
|
@ -517,4 +518,5 @@ Simulation {
|
|||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
..
|
||||
}
|
|
@ -78,71 +78,72 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:6:1
|
||||
0: Copy {
|
||||
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
1: Const {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
value: 1,
|
||||
dest: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
value: 0x1,
|
||||
},
|
||||
2: Add {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
|
||||
lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
3: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
|
||||
dest_width: 4,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
4: Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
5: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
|
||||
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
6: Const {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 3,
|
||||
dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 0x3,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
7: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
|
||||
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
|
||||
},
|
||||
8: AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
9: BranchIfSmallZero {
|
||||
target: 14,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
10: BranchIfSmallNonZero {
|
||||
target: 13,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
11: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
},
|
||||
12: Branch {
|
||||
target: 14,
|
||||
},
|
||||
13: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
14: NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
14: XorSmallImmediate {
|
||||
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: 0x1,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
15: Return,
|
||||
|
@ -156,7 +157,7 @@ Simulation {
|
|||
},
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
|
@ -498,4 +499,5 @@ Simulation {
|
|||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
..
|
||||
}
|
|
@ -398,476 +398,477 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
0: Const {
|
||||
dest: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 0,
|
||||
dest: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 0x0,
|
||||
},
|
||||
1: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
|
||||
start: 2,
|
||||
len: 2,
|
||||
},
|
||||
2: CastToSInt {
|
||||
dest: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest_width: 2,
|
||||
},
|
||||
3: Const {
|
||||
dest: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
value: 2,
|
||||
dest: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
value: 0x2,
|
||||
},
|
||||
4: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
|
||||
start: 1,
|
||||
len: 1,
|
||||
},
|
||||
5: Copy {
|
||||
dest: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
6: Copy {
|
||||
dest: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
7: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
|
||||
start: 0,
|
||||
len: 1,
|
||||
},
|
||||
8: Copy {
|
||||
dest: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
9: Copy {
|
||||
dest: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
10: Copy {
|
||||
dest: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
11: Copy {
|
||||
dest: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: ".1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
12: Copy {
|
||||
dest: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
13: Copy {
|
||||
dest: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
14: Copy {
|
||||
dest: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
},
|
||||
15: Copy {
|
||||
dest: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
},
|
||||
16: Copy {
|
||||
dest: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
|
||||
},
|
||||
17: Copy {
|
||||
dest: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
18: Copy {
|
||||
dest: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
},
|
||||
19: Copy {
|
||||
dest: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
},
|
||||
20: Copy {
|
||||
dest: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
},
|
||||
21: Shl {
|
||||
dest: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
|
||||
rhs: 1,
|
||||
},
|
||||
22: Or {
|
||||
dest: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
23: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
|
||||
dest_width: 2,
|
||||
},
|
||||
24: Shl {
|
||||
dest: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: 2,
|
||||
},
|
||||
25: Or {
|
||||
dest: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
26: Shl {
|
||||
dest: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
lhs: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
|
||||
lhs: StatePartIndex<BigSlots>(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
rhs: 2,
|
||||
},
|
||||
27: Or {
|
||||
dest: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
lhs: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
lhs: StatePartIndex<BigSlots>(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
|
||||
},
|
||||
28: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
src: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
src: StatePartIndex<BigSlots>(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest_width: 6,
|
||||
},
|
||||
29: Copy {
|
||||
dest: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
},
|
||||
30: Const {
|
||||
dest: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
value: 1,
|
||||
dest: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
|
||||
value: 0x1,
|
||||
},
|
||||
31: CmpEq {
|
||||
dest: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
32: Copy {
|
||||
dest: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
33: Copy {
|
||||
dest: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
},
|
||||
34: Copy {
|
||||
dest: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: ".1", ty: Bool },
|
||||
},
|
||||
35: Copy {
|
||||
dest: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
|
||||
},
|
||||
36: Shl {
|
||||
dest: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
rhs: 1,
|
||||
},
|
||||
37: Or {
|
||||
dest: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
38: Shl {
|
||||
dest: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: 2,
|
||||
},
|
||||
39: Or {
|
||||
dest: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
40: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
src: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
|
||||
src: StatePartIndex<BigSlots>(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest_width: 6,
|
||||
},
|
||||
41: Copy {
|
||||
dest: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
|
||||
},
|
||||
42: Const {
|
||||
dest: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
value: 0,
|
||||
dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
||||
value: 0x0,
|
||||
},
|
||||
43: CmpEq {
|
||||
dest: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
44: Copy {
|
||||
dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
dest: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
src: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
},
|
||||
45: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
start: 2,
|
||||
len: 2,
|
||||
},
|
||||
46: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
start: 0,
|
||||
len: 1,
|
||||
},
|
||||
47: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
start: 1,
|
||||
len: 1,
|
||||
},
|
||||
48: Copy {
|
||||
dest: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
49: Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
50: Copy {
|
||||
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: ".1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
51: Copy {
|
||||
dest: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: ".1", ty: Bool },
|
||||
},
|
||||
52: Shl {
|
||||
dest: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
rhs: 1,
|
||||
},
|
||||
53: Or {
|
||||
dest: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
54: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest_width: 4,
|
||||
},
|
||||
55: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
|
||||
start: 2,
|
||||
len: 4,
|
||||
},
|
||||
56: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
start: 0,
|
||||
len: 2,
|
||||
},
|
||||
57: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
start: 0,
|
||||
len: 1,
|
||||
},
|
||||
58: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
start: 1,
|
||||
len: 1,
|
||||
},
|
||||
59: Copy {
|
||||
dest: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
60: Copy {
|
||||
dest: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
61: SliceInt {
|
||||
dest: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
start: 2,
|
||||
len: 2,
|
||||
},
|
||||
62: CastToSInt {
|
||||
dest: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest_width: 2,
|
||||
},
|
||||
63: Copy {
|
||||
dest: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
|
||||
},
|
||||
64: Copy {
|
||||
dest: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
|
||||
},
|
||||
65: Copy {
|
||||
dest: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
|
||||
},
|
||||
66: Shl {
|
||||
dest: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
dest: StatePartIndex<BigSlots>(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
|
||||
rhs: 1,
|
||||
},
|
||||
67: Or {
|
||||
dest: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
lhs: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
|
||||
rhs: StatePartIndex<BigSlots>(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
68: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
|
||||
dest_width: 2,
|
||||
},
|
||||
69: Shl {
|
||||
dest: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: 2,
|
||||
},
|
||||
70: Or {
|
||||
dest: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
lhs: StatePartIndex<BigSlots>(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
|
||||
rhs: StatePartIndex<BigSlots>(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:8:1
|
||||
71: AndBigWithSmallImmediate {
|
||||
dest: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
lhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
rhs: 3,
|
||||
dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
lhs: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
rhs: 0x3,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:15:1
|
||||
72: BranchIfSmallNeImmediate {
|
||||
target: 75,
|
||||
lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
rhs: 0,
|
||||
lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
rhs: 0x0,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:16:1
|
||||
73: Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:17:1
|
||||
74: Copy {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:15:1
|
||||
75: BranchIfSmallNeImmediate {
|
||||
target: 78,
|
||||
lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
rhs: 1,
|
||||
lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
rhs: 0x1,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:18:1
|
||||
76: Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:19:1
|
||||
77: Copy {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:15:1
|
||||
78: BranchIfSmallNeImmediate {
|
||||
target: 81,
|
||||
lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
rhs: 2,
|
||||
lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
|
||||
rhs: 0x2,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:20:1
|
||||
79: Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
|
||||
src: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:21:1
|
||||
80: Copy {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:8:1
|
||||
81: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
|
||||
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
82: Const {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
value: 0,
|
||||
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
|
||||
value: 0x0,
|
||||
},
|
||||
83: Copy {
|
||||
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
|
||||
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:9:1
|
||||
84: BranchIfZero {
|
||||
target: 92,
|
||||
value: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:10:1
|
||||
85: BranchIfZero {
|
||||
target: 87,
|
||||
value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:11:1
|
||||
86: Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:10:1
|
||||
87: BranchIfNonZero {
|
||||
target: 92,
|
||||
value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:12:1
|
||||
88: BranchIfZero {
|
||||
target: 90,
|
||||
value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:13:1
|
||||
89: Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:12:1
|
||||
90: BranchIfNonZero {
|
||||
target: 92,
|
||||
value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:14:1
|
||||
91: Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:8:1
|
||||
92: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
|
||||
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
|
||||
},
|
||||
93: AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
94: BranchIfSmallZero {
|
||||
target: 99,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
95: BranchIfSmallNonZero {
|
||||
target: 98,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
96: Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
dest: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
},
|
||||
97: Branch {
|
||||
target: 99,
|
||||
},
|
||||
98: Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
dest: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
|
||||
},
|
||||
99: NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
99: XorSmallImmediate {
|
||||
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: 0x1,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
100: Return,
|
||||
|
@ -881,7 +882,7 @@ Simulation {
|
|||
},
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
|
@ -1638,4 +1639,5 @@ Simulation {
|
|||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
..
|
||||
}
|
2776
crates/fayalite/tests/sim/expected/memories.txt
Normal file
2776
crates/fayalite/tests/sim/expected/memories.txt
Normal file
File diff suppressed because it is too large
Load diff
408
crates/fayalite/tests/sim/expected/memories.vcd
Normal file
408
crates/fayalite/tests/sim/expected/memories.vcd
Normal file
|
@ -0,0 +1,408 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module memories $end
|
||||
$scope struct r $end
|
||||
$var wire 4 ! addr $end
|
||||
$var wire 1 " en $end
|
||||
$var wire 1 # clk $end
|
||||
$scope struct data $end
|
||||
$var wire 8 $ \0 $end
|
||||
$var wire 8 % \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct w $end
|
||||
$var wire 4 & addr $end
|
||||
$var wire 1 ' en $end
|
||||
$var wire 1 ( clk $end
|
||||
$scope struct data $end
|
||||
$var wire 8 ) \0 $end
|
||||
$var wire 8 * \1 $end
|
||||
$upscope $end
|
||||
$scope struct mask $end
|
||||
$var wire 1 + \0 $end
|
||||
$var wire 1 , \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct mem $end
|
||||
$scope struct contents $end
|
||||
$scope struct [0] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 9 \0 $end
|
||||
$var reg 8 I \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [1] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 : \0 $end
|
||||
$var reg 8 J \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [2] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 ; \0 $end
|
||||
$var reg 8 K \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [3] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 < \0 $end
|
||||
$var reg 8 L \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [4] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 = \0 $end
|
||||
$var reg 8 M \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [5] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 > \0 $end
|
||||
$var reg 8 N \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [6] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 ? \0 $end
|
||||
$var reg 8 O \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [7] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 @ \0 $end
|
||||
$var reg 8 P \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [8] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 A \0 $end
|
||||
$var reg 8 Q \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [9] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 B \0 $end
|
||||
$var reg 8 R \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [10] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 C \0 $end
|
||||
$var reg 8 S \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [11] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 D \0 $end
|
||||
$var reg 8 T \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [12] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 E \0 $end
|
||||
$var reg 8 U \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [13] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 F \0 $end
|
||||
$var reg 8 V \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [14] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 G \0 $end
|
||||
$var reg 8 W \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [15] $end
|
||||
$scope struct mem $end
|
||||
$var reg 8 H \0 $end
|
||||
$var reg 8 X \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct r0 $end
|
||||
$var wire 4 - addr $end
|
||||
$var wire 1 . en $end
|
||||
$var wire 1 / clk $end
|
||||
$scope struct data $end
|
||||
$var wire 8 0 \0 $end
|
||||
$var wire 8 1 \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct w1 $end
|
||||
$var wire 4 2 addr $end
|
||||
$var wire 1 3 en $end
|
||||
$var wire 1 4 clk $end
|
||||
$scope struct data $end
|
||||
$var wire 8 5 \0 $end
|
||||
$var wire 8 6 \1 $end
|
||||
$upscope $end
|
||||
$scope struct mask $end
|
||||
$var wire 1 7 \0 $end
|
||||
$var wire 1 8 \1 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
b1 9
|
||||
b100011 I
|
||||
b1 :
|
||||
b100011 J
|
||||
b1 ;
|
||||
b100011 K
|
||||
b1 <
|
||||
b100011 L
|
||||
b1 =
|
||||
b100011 M
|
||||
b1 >
|
||||
b100011 N
|
||||
b1 ?
|
||||
b100011 O
|
||||
b1 @
|
||||
b100011 P
|
||||
b1 A
|
||||
b100011 Q
|
||||
b1 B
|
||||
b100011 R
|
||||
b1 C
|
||||
b100011 S
|
||||
b1 D
|
||||
b100011 T
|
||||
b1 E
|
||||
b100011 U
|
||||
b1 F
|
||||
b100011 V
|
||||
b1 G
|
||||
b100011 W
|
||||
b1 H
|
||||
b100011 X
|
||||
b0 !
|
||||
0"
|
||||
0#
|
||||
b0 $
|
||||
b0 %
|
||||
b0 &
|
||||
0'
|
||||
0(
|
||||
b0 )
|
||||
b0 *
|
||||
0+
|
||||
0,
|
||||
b0 -
|
||||
0.
|
||||
0/
|
||||
b0 0
|
||||
b0 1
|
||||
b0 2
|
||||
03
|
||||
04
|
||||
b0 5
|
||||
b0 6
|
||||
07
|
||||
08
|
||||
$end
|
||||
#1000000
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#2000000
|
||||
1"
|
||||
0#
|
||||
b1 $
|
||||
b100011 %
|
||||
1'
|
||||
0(
|
||||
b10000 )
|
||||
b100000 *
|
||||
1+
|
||||
1,
|
||||
1.
|
||||
0/
|
||||
b1 0
|
||||
b100011 1
|
||||
13
|
||||
04
|
||||
b10000 5
|
||||
b100000 6
|
||||
17
|
||||
18
|
||||
#3000000
|
||||
b10000 9
|
||||
b100000 I
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
b10000 $
|
||||
b100000 %
|
||||
b10000 0
|
||||
b100000 1
|
||||
#4000000
|
||||
0#
|
||||
0(
|
||||
b110000 )
|
||||
b1000000 *
|
||||
0+
|
||||
0/
|
||||
04
|
||||
b110000 5
|
||||
b1000000 6
|
||||
07
|
||||
#5000000
|
||||
b10000 9
|
||||
b1000000 I
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
b1000000 %
|
||||
b1000000 1
|
||||
#6000000
|
||||
0#
|
||||
0(
|
||||
b1010000 )
|
||||
b1100000 *
|
||||
1+
|
||||
0,
|
||||
0/
|
||||
04
|
||||
b1010000 5
|
||||
b1100000 6
|
||||
17
|
||||
08
|
||||
#7000000
|
||||
b1010000 9
|
||||
b1000000 I
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
b1010000 $
|
||||
b1010000 0
|
||||
#8000000
|
||||
0#
|
||||
0(
|
||||
b1110000 )
|
||||
b10000000 *
|
||||
0+
|
||||
0/
|
||||
04
|
||||
b1110000 5
|
||||
b10000000 6
|
||||
07
|
||||
#9000000
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#10000000
|
||||
0#
|
||||
0'
|
||||
0(
|
||||
b10010000 )
|
||||
b10100000 *
|
||||
0/
|
||||
03
|
||||
04
|
||||
b10010000 5
|
||||
b10100000 6
|
||||
#11000000
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#12000000
|
||||
0#
|
||||
b1 &
|
||||
1'
|
||||
0(
|
||||
1+
|
||||
1,
|
||||
0/
|
||||
b1 2
|
||||
13
|
||||
04
|
||||
17
|
||||
18
|
||||
#13000000
|
||||
b10010000 :
|
||||
b10100000 J
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#14000000
|
||||
0#
|
||||
b10 &
|
||||
0(
|
||||
b10110000 )
|
||||
b11000000 *
|
||||
0/
|
||||
b10 2
|
||||
04
|
||||
b10110000 5
|
||||
b11000000 6
|
||||
#15000000
|
||||
b10110000 ;
|
||||
b11000000 K
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#16000000
|
||||
0#
|
||||
0'
|
||||
0(
|
||||
b11010000 )
|
||||
b11100000 *
|
||||
0/
|
||||
03
|
||||
04
|
||||
b11010000 5
|
||||
b11100000 6
|
||||
#17000000
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#18000000
|
||||
b1 !
|
||||
0#
|
||||
b10010000 $
|
||||
b10100000 %
|
||||
0(
|
||||
b1 -
|
||||
0/
|
||||
b10010000 0
|
||||
b10100000 1
|
||||
04
|
||||
#19000000
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#20000000
|
||||
b10 !
|
||||
0#
|
||||
b10110000 $
|
||||
b11000000 %
|
||||
0(
|
||||
b10 -
|
||||
0/
|
||||
b10110000 0
|
||||
b11000000 1
|
||||
04
|
||||
#21000000
|
||||
1#
|
||||
1(
|
||||
1/
|
||||
14
|
||||
#22000000
|
||||
0#
|
||||
0(
|
||||
0/
|
||||
04
|
|
@ -93,86 +93,86 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
0: Copy {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
|
||||
},
|
||||
1: Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:2:1
|
||||
2: Copy {
|
||||
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
|
||||
},
|
||||
3: Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:1:1
|
||||
4: Const {
|
||||
dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 15,
|
||||
dest: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 0xf,
|
||||
},
|
||||
5: Const {
|
||||
dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 5,
|
||||
dest: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 0x5,
|
||||
},
|
||||
6: CmpLt {
|
||||
dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
},
|
||||
7: CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
|
||||
dest_width: 4,
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:7:1
|
||||
8: Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:8:1
|
||||
9: BranchIfZero {
|
||||
target: 11,
|
||||
value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:9:1
|
||||
10: Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:2:1
|
||||
11: Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
12: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:1:1
|
||||
13: CastToSInt {
|
||||
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
dest: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
dest_width: 2,
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:6:1
|
||||
14: Copy {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:2:1
|
||||
15: Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
16: Copy {
|
||||
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
|
||||
dest: StatePartIndex<BigSlots>(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
17: Return,
|
||||
|
@ -806,4 +806,5 @@ Simulation {
|
|||
],
|
||||
instant: 2 μs,
|
||||
clocks_triggered: [],
|
||||
..
|
||||
}
|
|
@ -94,132 +94,133 @@ Simulation {
|
|||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:13:1
|
||||
0: Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:12:1
|
||||
1: Copy {
|
||||
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:10:1
|
||||
2: Copy {
|
||||
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:8:1
|
||||
3: Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:6:1
|
||||
4: Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
5: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
|
||||
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
6: Const {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
value: 0,
|
||||
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
value: 0x0,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
7: IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
|
||||
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
|
||||
},
|
||||
8: AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
9: BranchIfSmallZero {
|
||||
target: 14,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
10: BranchIfSmallNonZero {
|
||||
target: 13,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
11: Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
||||
},
|
||||
12: Branch {
|
||||
target: 14,
|
||||
},
|
||||
13: Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:7:1
|
||||
14: BranchIfSmallZero {
|
||||
target: 19,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
15: BranchIfSmallNonZero {
|
||||
target: 18,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
16: Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
||||
},
|
||||
17: Branch {
|
||||
target: 19,
|
||||
},
|
||||
18: Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:9:1
|
||||
19: BranchIfSmallZero {
|
||||
target: 24,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
20: BranchIfSmallNonZero {
|
||||
target: 23,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
21: Copy {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
||||
},
|
||||
22: Branch {
|
||||
target: 24,
|
||||
},
|
||||
23: Copy {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:11:1
|
||||
24: BranchIfSmallZero {
|
||||
target: 29,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
25: BranchIfSmallNonZero {
|
||||
target: 28,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
26: Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
||||
},
|
||||
27: Branch {
|
||||
target: 29,
|
||||
},
|
||||
28: Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
29: NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
29: XorSmallImmediate {
|
||||
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
||||
rhs: 0x1,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
30: Return,
|
||||
|
@ -233,7 +234,7 @@ Simulation {
|
|||
},
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
|
@ -678,4 +679,5 @@ Simulation {
|
|||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
..
|
||||
}
|
Loading…
Reference in a new issue