WIP adding VCD output
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SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
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@ -46,6 +46,7 @@ use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops
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mod interpreter;
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pub mod time;
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pub mod vcd;
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#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
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enum CondBody {
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@ -2,7 +2,7 @@
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// See Notices.txt for copyright information
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use std::{
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fmt,
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ops::{Add, AddAssign},
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ops::{Add, AddAssign, Sub, SubAssign},
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time::Duration,
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};
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@ -11,9 +11,43 @@ pub struct SimInstant {
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time_since_start: SimDuration,
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}
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impl SimInstant {
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pub const fn checked_add(self, duration: SimDuration) -> Option<Self> {
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let Some(time_since_start) = self.time_since_start.checked_add(duration) else {
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return None;
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};
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Some(SimInstant { time_since_start })
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}
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pub const fn checked_duration_since(self, earlier: Self) -> Option<SimDuration> {
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self.time_since_start.checked_sub(earlier.time_since_start)
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}
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pub const fn checked_sub(self, duration: SimDuration) -> Option<Self> {
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let Some(time_since_start) = self.time_since_start.checked_sub(duration) else {
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return None;
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};
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Some(SimInstant { time_since_start })
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}
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#[track_caller]
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pub const fn duration_since(self, earlier: Self) -> SimDuration {
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let Some(retval) = self.checked_duration_since(earlier) else {
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panic!(
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"tried to compute the duration since a later time -- durations can't be negative"
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);
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};
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retval
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}
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pub const fn saturating_duration_since(self, earlier: Self) -> SimDuration {
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let Some(retval) = self.checked_duration_since(earlier) else {
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return SimDuration::ZERO;
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};
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retval
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}
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}
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impl Add<SimDuration> for SimInstant {
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type Output = SimInstant;
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#[track_caller]
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fn add(mut self, rhs: SimDuration) -> Self::Output {
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self += rhs;
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self
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@ -21,6 +55,7 @@ impl Add<SimDuration> for SimInstant {
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}
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impl AddAssign<SimDuration> for SimInstant {
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#[track_caller]
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fn add_assign(&mut self, rhs: SimDuration) {
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self.time_since_start += rhs;
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}
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@ -29,11 +64,40 @@ impl AddAssign<SimDuration> for SimInstant {
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impl Add<SimInstant> for SimDuration {
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type Output = SimInstant;
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#[track_caller]
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fn add(self, rhs: SimInstant) -> Self::Output {
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rhs.add(self)
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}
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}
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impl Sub for SimInstant {
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type Output = SimDuration;
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#[track_caller]
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fn sub(self, rhs: SimInstant) -> Self::Output {
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self.duration_since(rhs)
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}
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}
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impl Sub<SimDuration> for SimInstant {
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type Output = SimInstant;
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#[track_caller]
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fn sub(self, rhs: SimDuration) -> Self::Output {
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let Some(retval) = self.checked_sub(rhs) else {
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panic!("SimInstant underflow");
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};
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retval
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}
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}
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impl SubAssign<SimDuration> for SimInstant {
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#[track_caller]
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fn sub_assign(&mut self, rhs: SimDuration) {
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*self = *self - rhs;
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}
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}
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impl SimInstant {
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pub const START: SimInstant = SimInstant {
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time_since_start: SimDuration::ZERO,
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@ -52,6 +116,7 @@ pub struct SimDuration {
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}
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impl AddAssign for SimDuration {
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#[track_caller]
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fn add_assign(&mut self, rhs: SimDuration) {
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*self = *self + rhs;
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}
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@ -60,6 +125,7 @@ impl AddAssign for SimDuration {
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impl Add for SimDuration {
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type Output = SimDuration;
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#[track_caller]
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fn add(self, rhs: SimDuration) -> Self::Output {
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SimDuration {
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attos: self
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@ -70,6 +136,27 @@ impl Add for SimDuration {
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}
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}
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impl Sub for SimDuration {
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type Output = Self;
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#[track_caller]
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fn sub(self, rhs: Self) -> Self::Output {
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SimDuration {
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attos: self
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.attos
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.checked_add(rhs.attos)
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.expect("underflow subtracting durations -- durations can't be negative"),
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}
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}
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}
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impl SubAssign for SimDuration {
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#[track_caller]
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fn sub_assign(&mut self, rhs: Self) {
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*self = *self - rhs;
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}
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}
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#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
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pub struct SimDurationParts {
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pub attos: u16,
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@ -84,7 +171,7 @@ pub struct SimDurationParts {
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macro_rules! impl_duration_units {
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(
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$(
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#[unit_const = $UNIT:ident, from_units = $from_units:ident, units = $units:ident, suffix = $suffix:literal]
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#[unit_const = $UNIT:ident, from_units = $from_units:ident, as_units = $as_units:ident, units = $units:ident, suffix = $suffix:literal]
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const $log10_units_per_sec:ident: u32 = $log10_units_per_sec_value:expr;
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)*
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) => {
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@ -94,8 +181,11 @@ macro_rules! impl_duration_units {
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pub const fn $from_units($units: u128) -> Self {
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Self::from_units_helper::<{ Self::$log10_units_per_sec }>($units)
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}
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pub const fn $as_units(self) -> u128 {
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self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }
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}
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)*
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pub const fn into_parts(mut self) -> SimDurationParts {
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pub const fn to_parts(mut self) -> SimDurationParts {
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$(
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let $units = self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
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self.attos %= const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
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@ -176,19 +266,19 @@ macro_rules! impl_duration_units {
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}
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impl_duration_units! {
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#[unit_const = SECOND, from_units = from_secs, units = secs, suffix = "s"]
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#[unit_const = SECOND, from_units = from_secs, as_units = as_secs, units = secs, suffix = "s"]
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const LOG10_SECS_PER_SEC: u32 = 0;
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#[unit_const = MILLISECOND, from_units = from_millis, units = millis, suffix = "ms"]
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#[unit_const = MILLISECOND, from_units = from_millis, as_units = as_millis, units = millis, suffix = "ms"]
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const LOG10_MILLIS_PER_SEC: u32 = 3;
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#[unit_const = MICROSECOND, from_units = from_micros, units = micros, suffix = "μs"]
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#[unit_const = MICROSECOND, from_units = from_micros, as_units = as_micros, units = micros, suffix = "μs"]
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const LOG10_MICROS_PER_SEC: u32 = 6;
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#[unit_const = NANOSECOND, from_units = from_nanos, units = nanos, suffix = "ns"]
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#[unit_const = NANOSECOND, from_units = from_nanos, as_units = as_nanos, units = nanos, suffix = "ns"]
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const LOG10_NANOS_PER_SEC: u32 = 9;
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#[unit_const = PICOSECOND, from_units = from_picos, units = picos, suffix = "ps"]
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#[unit_const = PICOSECOND, from_units = from_picos, as_units = as_picos, units = picos, suffix = "ps"]
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const LOG10_PICOS_PER_SEC: u32 = 12;
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#[unit_const = FEMTOSECOND, from_units = from_femtos, units = femtos, suffix = "fs"]
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#[unit_const = FEMTOSECOND, from_units = from_femtos, as_units = as_femtos, units = femtos, suffix = "fs"]
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const LOG10_FEMTOS_PER_SEC: u32 = 15;
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#[unit_const = ATTOSECOND, from_units = from_attos, units = attos, suffix = "as"]
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#[unit_const = ATTOSECOND, from_units = from_attos, as_units = as_attos, units = attos, suffix = "as"]
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const LOG10_ATTOS_PER_SEC: u32 = 18;
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}
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@ -208,6 +298,96 @@ impl SimDuration {
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None => panic!("duration too big"),
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}
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}
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pub const fn abs_diff(self, other: Self) -> Self {
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Self {
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attos: self.attos.abs_diff(other.attos),
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}
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}
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pub const fn checked_add(self, rhs: Self) -> Option<Self> {
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let Some(attos) = self.attos.checked_add(rhs.attos) else {
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return None;
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};
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Some(Self { attos })
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}
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pub const fn checked_sub(self, rhs: Self) -> Option<Self> {
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let Some(attos) = self.attos.checked_sub(rhs.attos) else {
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return None;
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};
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Some(Self { attos })
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}
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pub const fn is_zero(self) -> bool {
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self.attos == 0
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}
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pub const fn saturating_add(self, rhs: Self) -> Self {
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Self {
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attos: self.attos.saturating_add(rhs.attos),
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}
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}
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pub const fn saturating_sub(self, rhs: Self) -> Self {
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Self {
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attos: self.attos.saturating_sub(rhs.attos),
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}
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}
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pub const fn checked_ilog10(self) -> Option<i32> {
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let Some(ilog10_attos) = self.attos.checked_ilog10() else {
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return None;
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};
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Some(ilog10_attos as i32 - Self::LOG10_ATTOS_PER_SEC as i32)
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}
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#[track_caller]
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pub const fn ilog10(self) -> i32 {
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let Some(retval) = self.checked_ilog10() else {
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panic!("tried to take the ilog10 of 0");
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};
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retval
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}
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pub const fn checked_pow10(log10: i32, underflow_is_zero: bool) -> Option<Self> {
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let Some(log10) = Self::LOG10_ATTOS_PER_SEC.checked_add_signed(log10) else {
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return if log10 < 0 && underflow_is_zero {
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Some(Self::ZERO)
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} else {
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None
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};
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};
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let Some(attos) = 10u128.checked_pow(log10) else {
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return None;
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};
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Some(Self { attos })
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}
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#[track_caller]
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pub const fn pow10(log10: i32) -> Self {
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let Some(retval) = Self::checked_pow10(log10, true) else {
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panic!("pow10 overflowed");
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};
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retval
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}
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pub const fn is_power_of_ten(self) -> bool {
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const TEN: u128 = 10;
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const NUMBER_OF_POWERS_OF_TEN: usize = {
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let mut n = 0;
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while let Some(_) = TEN.checked_pow(n as u32) {
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n += 1;
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}
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n
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};
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const POWERS_OF_TEN: [u128; NUMBER_OF_POWERS_OF_TEN] = {
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let mut retval = [0; NUMBER_OF_POWERS_OF_TEN];
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let mut i = 0;
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while i < NUMBER_OF_POWERS_OF_TEN {
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retval[i] = TEN.pow(i as u32);
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i += 1;
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}
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retval
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};
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let mut i = 0;
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while i < NUMBER_OF_POWERS_OF_TEN {
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if self.attos == POWERS_OF_TEN[i] {
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return true;
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}
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i += 1;
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}
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false
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}
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}
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impl From<Duration> for SimDuration {
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542
crates/fayalite/src/sim/vcd.rs
Normal file
542
crates/fayalite/src/sim/vcd.rs
Normal file
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@ -0,0 +1,542 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use crate::{
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expr::Flow,
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int::UInt,
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sim::{
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time::{SimDuration, SimInstant},
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TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
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TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
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TraceMemPort, TraceModule, TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId,
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TraceScope, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
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},
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};
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use bitvec::slice::BitSlice;
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use std::{fmt, io, mem};
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pub struct VcdWriterDecls<W: io::Write + 'static> {
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writer: W,
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timescale: SimDuration,
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}
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impl<W: io::Write + 'static> VcdWriterDecls<W> {
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pub fn new(writer: W) -> Self {
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Self {
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writer,
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timescale: SimDuration::from_picos(1),
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}
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}
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pub fn timescale(&self) -> SimDuration {
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self.timescale
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}
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#[track_caller]
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pub fn with_timescale(mut self, timescale: SimDuration) -> Self {
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// check timescale validity
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vcd_timescale(timescale);
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self.timescale = timescale;
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self
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}
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}
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#[track_caller]
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const fn vcd_timescale(timescale: SimDuration) -> &'static str {
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if !timescale.is_power_of_ten() {
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panic!("VCD timescale must be a power of 10");
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}
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macro_rules! timescales {
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($($const_name:ident = ($dur:expr, $text:literal),)*) => {
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$(const $const_name: SimDuration = $dur;)*
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match timescale {
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$($const_name => $text,)*
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_ => panic!("VCD timescale is too big"),
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}
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};
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}
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timescales! {
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TIMESCALE_1_AS = (SimDuration::from_attos(1), "1 as"),
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TIMESCALE_10_AS = (SimDuration::from_attos(10), "10 as"),
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TIMESCALE_100_AS = (SimDuration::from_attos(100), "100 as"),
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TIMESCALE_1_FS = (SimDuration::from_femtos(1), "1 fs"),
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TIMESCALE_10_FS = (SimDuration::from_femtos(10), "10 fs"),
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TIMESCALE_100_FS = (SimDuration::from_femtos(100), "100 fs"),
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TIMESCALE_1_PS = (SimDuration::from_picos(1), "1 ps"),
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TIMESCALE_10_PS = (SimDuration::from_picos(10), "10 ps"),
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TIMESCALE_100_PS = (SimDuration::from_picos(100), "100 ps"),
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TIMESCALE_1_NS = (SimDuration::from_nanos(1), "1 ns"),
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TIMESCALE_10_NS = (SimDuration::from_nanos(10), "10 ns"),
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TIMESCALE_100_NS = (SimDuration::from_nanos(100), "100 ns"),
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TIMESCALE_1_US = (SimDuration::from_micros(1), "1 us"),
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TIMESCALE_10_US = (SimDuration::from_micros(10), "10 us"),
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TIMESCALE_100_US = (SimDuration::from_micros(100), "100 us"),
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TIMESCALE_1_MS = (SimDuration::from_millis(1), "1 ms"),
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TIMESCALE_10_MS = (SimDuration::from_millis(10), "10 ms"),
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TIMESCALE_100_MS = (SimDuration::from_millis(100), "100 ms"),
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TIMESCALE_1_S = (SimDuration::from_secs(1), "1 s"),
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TIMESCALE_10_S = (SimDuration::from_secs(10), "10 s"),
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TIMESCALE_100_S = (SimDuration::from_secs(100), "100 s"),
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TIMESCALE_1000_S = (SimDuration::from_secs(1000), "1000 s"),
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}
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}
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impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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let Self {
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writer: _,
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timescale,
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} = self;
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f.debug_struct("VcdWriterDecls")
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.field("timescale", timescale)
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.finish_non_exhaustive()
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}
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}
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fn write_vcd_scope<W: io::Write, R>(
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writer: &mut W,
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scope_type: &str,
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scope_name: &str,
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f: impl FnOnce(&mut W) -> io::Result<R>,
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) -> io::Result<R> {
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writeln!(writer, "$scope {scope_type} {scope_name} $end")?;
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let retval = f(writer)?;
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writeln!(writer, "$upscope $end")?;
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Ok(retval)
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}
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macro_rules! trait_arg {
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(
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trait $Arg:ident {
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$(
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fn $fn:ident(self) -> $ty:ty;
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)*
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}
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) => {
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trait $Arg: Sized {
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||||
$(fn $fn(self) -> $ty {
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unreachable!()
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})*
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}
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$(
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impl $Arg for $ty {
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fn $fn(self) -> $ty {
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self
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}
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}
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||||
)*
|
||||
};
|
||||
}
|
||||
|
||||
trait_arg! {
|
||||
trait Arg {
|
||||
fn module(self) -> ArgModule;
|
||||
fn module_body(self) -> ArgModuleBody;
|
||||
fn in_type(self) -> ArgInType;
|
||||
}
|
||||
}
|
||||
|
||||
struct ArgModule {}
|
||||
|
||||
struct ArgModuleBody {}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
struct ArgInType {
|
||||
source_var_type: &'static str,
|
||||
sink_var_type: &'static str,
|
||||
duplex_var_type: &'static str,
|
||||
}
|
||||
|
||||
trait WriteTrace: Copy {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()>;
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceDecl {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
match self {
|
||||
Self::Scope(v) => v.write_trace(writer, arg),
|
||||
Self::Scalar(v) => v.write_trace(writer, arg),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceScalar {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
match self {
|
||||
Self::UInt(v) => v.write_trace(writer, arg),
|
||||
Self::SInt(v) => v.write_trace(writer, arg),
|
||||
Self::Bool(v) => v.write_trace(writer, arg),
|
||||
Self::FieldlessEnum(v) => v.write_trace(writer, arg),
|
||||
Self::EnumDiscriminant(v) => v.write_trace(writer, arg),
|
||||
Self::Clock(v) => v.write_trace(writer, arg),
|
||||
Self::SyncReset(v) => v.write_trace(writer, arg),
|
||||
Self::AsyncReset(v) => v.write_trace(writer, arg),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn write_scalar_id<W: io::Write>(writer: &mut W, id: TraceScalarId) -> io::Result<()> {
|
||||
let min_char = b'!';
|
||||
let max_char = b'~';
|
||||
let base = (max_char - min_char + 1) as usize;
|
||||
let mut id = id.as_usize();
|
||||
loop {
|
||||
let digit = (id % base) as u8 + min_char;
|
||||
id /= base;
|
||||
writer.write_all(&[digit])?;
|
||||
if id == 0 {
|
||||
break;
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn write_vcd_var<W: io::Write>(
|
||||
writer: &mut W,
|
||||
var_type: &str,
|
||||
size: usize,
|
||||
id: TraceScalarId,
|
||||
name: &str,
|
||||
) -> io::Result<()> {
|
||||
write!(writer, "$var {var_type} {size} ")?;
|
||||
write_scalar_id(writer, id)?;
|
||||
writeln!(writer, " {name} $end")
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceUInt {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let ArgInType {
|
||||
source_var_type,
|
||||
sink_var_type,
|
||||
duplex_var_type,
|
||||
} = arg.in_type();
|
||||
let Self { id, name, ty, flow } = self;
|
||||
let var_type = match flow {
|
||||
Flow::Source => source_var_type,
|
||||
Flow::Sink => sink_var_type,
|
||||
Flow::Duplex => duplex_var_type,
|
||||
};
|
||||
if ty.width() == 0 {
|
||||
write_vcd_var(writer, "string", ty.width(), id, &name)
|
||||
} else {
|
||||
write_vcd_var(writer, var_type, ty.width(), id, &name)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceSInt {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let Self { id, name, ty, flow } = self;
|
||||
TraceUInt {
|
||||
id,
|
||||
name,
|
||||
ty: UInt::new_dyn(ty.width()),
|
||||
flow,
|
||||
}
|
||||
.write_trace(writer, arg)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceBool {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let Self { id, name, flow } = self;
|
||||
TraceUInt {
|
||||
id,
|
||||
name,
|
||||
flow,
|
||||
ty: UInt::new_dyn(1),
|
||||
}
|
||||
.write_trace(writer, arg)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceFieldlessEnum {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceEnumDiscriminant {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceClock {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let Self { id, name, flow } = self;
|
||||
TraceBool { id, name, flow }.write_trace(writer, arg)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceSyncReset {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let Self { id, name, flow } = self;
|
||||
TraceBool { id, name, flow }.write_trace(writer, arg)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceAsyncReset {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let Self { id, name, flow } = self;
|
||||
TraceBool { id, name, flow }.write_trace(writer, arg)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceScope {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
match self {
|
||||
Self::Module(v) => v.write_trace(writer, arg),
|
||||
Self::Instance(v) => v.write_trace(writer, arg),
|
||||
Self::MemPort(v) => v.write_trace(writer, arg),
|
||||
Self::Wire(v) => v.write_trace(writer, arg),
|
||||
Self::Reg(v) => v.write_trace(writer, arg),
|
||||
Self::ModuleIO(v) => v.write_trace(writer, arg),
|
||||
Self::Bundle(v) => v.write_trace(writer, arg),
|
||||
Self::Array(v) => v.write_trace(writer, arg),
|
||||
Self::EnumWithFields(v) => v.write_trace(writer, arg),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceModule {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let ArgModule {} = arg.module();
|
||||
let Self { name, children } = self;
|
||||
write_vcd_scope(writer, "module", &name, |writer| {
|
||||
for child in children {
|
||||
child.write_trace(writer, ArgModuleBody {})?;
|
||||
}
|
||||
Ok(())
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceInstance {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let ArgModuleBody {} = arg.module_body();
|
||||
let Self {
|
||||
name: _,
|
||||
instance_io,
|
||||
module,
|
||||
ty: _,
|
||||
} = self;
|
||||
instance_io.write_trace(
|
||||
writer,
|
||||
ArgInType {
|
||||
source_var_type: "wire",
|
||||
sink_var_type: "wire",
|
||||
duplex_var_type: "wire",
|
||||
},
|
||||
)?;
|
||||
module.write_trace(writer, ArgModule {})
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceMemPort {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceWire {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let ArgModuleBody {} = arg.module_body();
|
||||
let Self {
|
||||
name: _,
|
||||
child,
|
||||
ty: _,
|
||||
} = self;
|
||||
child.write_trace(
|
||||
writer,
|
||||
ArgInType {
|
||||
source_var_type: "wire",
|
||||
sink_var_type: "wire",
|
||||
duplex_var_type: "wire",
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceReg {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let ArgModuleBody {} = arg.module_body();
|
||||
let Self {
|
||||
name: _,
|
||||
child,
|
||||
ty: _,
|
||||
} = self;
|
||||
child.write_trace(
|
||||
writer,
|
||||
ArgInType {
|
||||
source_var_type: "reg",
|
||||
sink_var_type: "reg",
|
||||
duplex_var_type: "reg",
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceModuleIO {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let ArgModuleBody {} = arg.module_body();
|
||||
let Self {
|
||||
name: _,
|
||||
child,
|
||||
ty: _,
|
||||
flow: _,
|
||||
} = self;
|
||||
child.write_trace(
|
||||
writer,
|
||||
ArgInType {
|
||||
source_var_type: "wire",
|
||||
sink_var_type: "wire",
|
||||
duplex_var_type: "wire",
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceBundle {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let arg = arg.in_type();
|
||||
let Self {
|
||||
name,
|
||||
fields,
|
||||
ty: _,
|
||||
flow: _,
|
||||
} = self;
|
||||
write_vcd_scope(writer, "struct", &name, |writer| {
|
||||
for field in fields {
|
||||
field.write_trace(writer, arg)?;
|
||||
}
|
||||
Ok(())
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceArray {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
let arg = arg.in_type();
|
||||
let Self {
|
||||
name,
|
||||
elements,
|
||||
ty: _,
|
||||
flow: _,
|
||||
} = self;
|
||||
write_vcd_scope(writer, "struct", &name, |writer| {
|
||||
for element in elements {
|
||||
element.write_trace(writer, arg)?;
|
||||
}
|
||||
Ok(())
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl WriteTrace for TraceEnumWithFields {
|
||||
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
|
||||
todo!()
|
||||
}
|
||||
}
|
||||
|
||||
impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
|
||||
type Error = io::Error;
|
||||
type TraceWriter = VcdWriter<W>;
|
||||
|
||||
fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
|
||||
let Self {
|
||||
mut writer,
|
||||
timescale,
|
||||
} = self;
|
||||
writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
|
||||
module.write_trace(&mut writer, ArgModule {})?;
|
||||
writeln!(writer, "$enddefinitions $end")?;
|
||||
writeln!(writer, "$dumpvars")?;
|
||||
Ok(VcdWriter {
|
||||
writer,
|
||||
finished_init: false,
|
||||
timescale,
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
pub struct VcdWriter<W: io::Write + 'static> {
|
||||
writer: W,
|
||||
finished_init: bool,
|
||||
timescale: SimDuration,
|
||||
}
|
||||
|
||||
impl<W: io::Write + 'static> VcdWriter<W> {
|
||||
pub fn timescale(&self) -> SimDuration {
|
||||
self.timescale
|
||||
}
|
||||
}
|
||||
|
||||
impl<W: io::Write> TraceWriter for VcdWriter<W> {
|
||||
type Error = io::Error;
|
||||
|
||||
fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
|
||||
match value.len() {
|
||||
0 => self.writer.write_all(b"s0 ")?,
|
||||
1 => write!(self.writer, "{} ", if value[0] { "1" } else { "0" })?,
|
||||
_ => {
|
||||
self.writer.write_all(b"b")?;
|
||||
let mut any_ones = false;
|
||||
for bit in value.iter().rev() {
|
||||
if *bit {
|
||||
any_ones = true;
|
||||
self.writer.write_all(b"1")?;
|
||||
} else if any_ones {
|
||||
self.writer.write_all(b"0")?;
|
||||
}
|
||||
}
|
||||
if !any_ones {
|
||||
self.writer.write_all(b"0")?;
|
||||
}
|
||||
self.writer.write_all(b" ")?;
|
||||
}
|
||||
}
|
||||
write_scalar_id(&mut self.writer, id)?;
|
||||
self.writer.write_all(b"\n")
|
||||
}
|
||||
|
||||
fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
|
||||
self.set_signal_uint(id, value)
|
||||
}
|
||||
|
||||
fn finish_init(&mut self) -> Result<(), Self::Error> {
|
||||
if mem::replace(&mut self.finished_init, true) {
|
||||
return Ok(());
|
||||
}
|
||||
writeln!(self.writer, "$end")
|
||||
}
|
||||
|
||||
fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
|
||||
assert!(self.finished_init);
|
||||
let mut instant_attos = (instant - SimInstant::START).as_attos();
|
||||
instant_attos += self.timescale.as_attos() / 2;
|
||||
let timestamp = instant_attos / self.timescale.as_attos();
|
||||
writeln!(self.writer, "#{timestamp}")
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
self.writer.flush()
|
||||
}
|
||||
|
||||
fn close(mut self) -> Result<(), Self::Error> {
|
||||
self.writer.flush()
|
||||
}
|
||||
}
|
||||
|
||||
impl<W: io::Write> fmt::Debug for VcdWriter<W> {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
let Self {
|
||||
writer: _,
|
||||
finished_init,
|
||||
timescale,
|
||||
} = self;
|
||||
f.debug_struct("VcdWriter")
|
||||
.field("finished_init", finished_init)
|
||||
.field("timescale", timescale)
|
||||
.finish_non_exhaustive()
|
||||
}
|
||||
}
|
||||
|
|
@ -25,7 +25,7 @@ pub use scoped_ref::ScopedRef;
|
|||
#[doc(inline)]
|
||||
pub use misc::{
|
||||
get_many_mut, interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay,
|
||||
DebugAsRawString, MakeMutSlice,
|
||||
DebugAsRawString, MakeMutSlice, RcWriter,
|
||||
};
|
||||
|
||||
pub mod job_server;
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
use crate::intern::{Intern, Interned};
|
||||
use bitvec::{bits, order::Lsb0, slice::BitSlice, view::BitView};
|
||||
use std::{
|
||||
cell::Cell,
|
||||
fmt::{self, Debug, Write},
|
||||
rc::Rc,
|
||||
sync::{Arc, OnceLock},
|
||||
|
|
@ -177,3 +178,50 @@ pub fn get_many_mut<T, const N: usize>(slice: &mut [T], indexes: [usize; N]) ->
|
|||
std::array::from_fn(|i| &mut *base.add(indexes[i]))
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Default)]
|
||||
pub struct RcWriter(Rc<Cell<Vec<u8>>>);
|
||||
|
||||
impl Debug for RcWriter {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
self.borrow_impl(|buf| {
|
||||
f.debug_tuple("RcWriter")
|
||||
.field(&DebugAsDisplay(format_args!("b\"{}\"", buf.escape_ascii())))
|
||||
.finish()
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl RcWriter {
|
||||
fn borrow_impl<R>(&self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
|
||||
let buf = Cell::take(&self.0);
|
||||
struct PutBackOnDrop<'a> {
|
||||
buf: Vec<u8>,
|
||||
this: &'a RcWriter,
|
||||
}
|
||||
impl Drop for PutBackOnDrop<'_> {
|
||||
fn drop(&mut self) {
|
||||
self.this.0.set(std::mem::take(&mut self.buf));
|
||||
}
|
||||
}
|
||||
let mut buf = PutBackOnDrop { buf, this: self };
|
||||
f(&mut buf.buf)
|
||||
}
|
||||
pub fn borrow<R>(&mut self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
|
||||
self.borrow_impl(f)
|
||||
}
|
||||
pub fn take(&mut self) -> Vec<u8> {
|
||||
Cell::take(&self.0)
|
||||
}
|
||||
}
|
||||
|
||||
impl std::io::Write for RcWriter {
|
||||
fn write(&mut self, buf: &[u8]) -> std::io::Result<usize> {
|
||||
self.borrow(|v| v.extend_from_slice(buf));
|
||||
Ok(buf.len())
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> std::io::Result<()> {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,11 @@
|
|||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
// See Notices.txt for copyright information
|
||||
use fayalite::{int::UIntValue, prelude::*, sim::Simulation};
|
||||
use fayalite::{
|
||||
int::UIntValue,
|
||||
prelude::*,
|
||||
sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
|
||||
util::RcWriter,
|
||||
};
|
||||
|
||||
#[hdl_module(outline_generated)]
|
||||
pub fn connect_const() {
|
||||
|
|
@ -177,14 +182,25 @@ pub fn mod1() {
|
|||
connect(o, child);
|
||||
}
|
||||
|
||||
#[cfg(todo)]
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_mod1() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let mut sim = Simulation::new(mod1());
|
||||
sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
|
||||
let mut writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
sim.write_bool_or_int(sim.io().o.i, 0x3_hdl_u4);
|
||||
sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
|
||||
sim.settle_step();
|
||||
sim.advance_time(SimDuration::from_micros(1));
|
||||
sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
|
||||
sim.advance_time(SimDuration::from_micros(1));
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
todo!("generated vcd is incorrect");
|
||||
if vcd != r#""# {
|
||||
panic!();
|
||||
}
|
||||
let sim_debug = format!("{sim:#?}");
|
||||
println!("#######\n{sim_debug}\n#######");
|
||||
if sim_debug
|
||||
|
|
|
|||
Loading…
Reference in a new issue