libre-chip/fayalite
2
0
Fork 2
Code Issues 1 Pull requests Actions Packages Projects Releases Wiki Activity

sim: WIP working on memory
All checks were successful
/ deps (push) Successful in 17s
Details
/ test (push) Successful in 5m18s
Details
/ deps (pull_request) Successful in 14s
Details
/ test (pull_request) Successful in 5m18s
Details

Browse source
This commit is contained in:
Jacob Lifshay 2024-12-06 15:53:34 -08:00
parent 3ed7827485
commit 9654167ca3
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 40 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

48
crates/fayalite/src/sim.rs
View file

@ -1215,10 +1215,16 @@ struct Register {
}
#[derive(Debug)]
enum MemoryPort {
ReadOnly {},
WriteOnly {},
ReadWrite {},
struct MemoryPort {
clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
addr_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
en_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
data: CompiledValue<CanonicalType>,
read_data_delayed: Vec<TypeIndex>,
write_data_delayed: Vec<TypeIndex>,
write_mask_delayed: Vec<TypeIndex>,
write_mode_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
}
#[derive(Debug)]
@ -3350,11 +3356,37 @@ impl Compiler {
};
self.decl_conditions.insert(target, conditions);
trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
todo!("handle read/write");
match port.port_kind() {
PortKind::ReadOnly => MemoryPort::ReadOnly {},
PortKind::WriteOnly => MemoryPort::WriteOnly {},
PortKind::ReadWrite => MemoryPort::ReadWrite {},
PortKind::ReadOnly => MemoryPort {
clk_triggered: todo!(),
addr_delayed: todo!(),
en_delayed: todo!(),
data: todo!(),
read_data_delayed: todo!(),
write_data_delayed: todo!(),
write_mask_delayed: todo!(),
write_mode_delayed: todo!(),
},
PortKind::WriteOnly => MemoryPort {
clk_triggered: todo!(),
addr_delayed: todo!(),
en_delayed: todo!(),
data: todo!(),
read_data_delayed: todo!(),
write_data_delayed: todo!(),
write_mask_delayed: todo!(),
write_mode_delayed: todo!(),
},
PortKind::ReadWrite => MemoryPort {
clk_triggered: todo!(),
addr_delayed: todo!(),
en_delayed: todo!(),
data: todo!(),
read_data_delayed: todo!(),
write_data_delayed: todo!(),
write_mask_delayed: todo!(),
write_mode_delayed: todo!(),
},
}
})
.collect();