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Jacob Lifshay 2af38de900
add more memory tests
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2024-12-13 15:04:48 -08:00
Jacob Lifshay c756aeec70
tests/sim: add test for memory rw port
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2024-12-12 20:50:41 -08:00
Jacob Lifshay 903ca1bf30
sim: simple memory test works!
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2024-12-12 19:47:57 -08:00
Jacob Lifshay 8d030ac65d
sim/interpreter: add addresses to instruction listing
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2024-12-12 16:25:38 -08:00
Jacob Lifshay 562c479b62
sim/interpreter: fix StatePartLayout name in debug output 2024-12-12 15:06:17 -08:00
Jacob Lifshay 393f78a14d
sim: add WIP memory test
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2024-12-11 23:28:15 -08:00
Jacob Lifshay 8616ee4737
tests/sim: test_enums works!
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2024-12-11 00:01:04 -08:00
Jacob Lifshay 5087f16099
sim: fix assignments graph by properly including conditions as assignment inputs 2024-12-11 00:00:21 -08:00
Jacob Lifshay 6b31e6d515
sim: add .dot output for Assignments graph for debugging
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2024-12-10 23:40:33 -08:00
Jacob Lifshay 564ccb30bc
sim/vcd: fix variable identifiers to follow verilog rules 2024-12-10 23:39:17 -08:00
Jacob Lifshay ca759168ff
tests/sim: add WIP test for enums 2024-12-10 23:37:26 -08:00
Jacob Lifshay e4cf66adf8
sim: implement memories, still needs testing
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2024-12-09 23:03:01 -08:00
Jacob Lifshay cd0dd7b7ee
change memory write latency to NonZeroUsize to match read latency being usize 2024-12-09 23:01:40 -08:00
Jacob Lifshay 9654167ca3
sim: WIP working on memory
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2024-12-06 15:53:34 -08:00
Jacob Lifshay 3ed7827485
sim: WIP adding memory support
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2024-12-05 21:35:23 -08:00
Jacob Lifshay e504cfebfe
add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference
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2024-12-05 20:32:15 -08:00
Jacob Lifshay 9f42cab471
change to version 0.3.0 for breaking change 2024-12-05 20:26:28 -08:00
Jacob Lifshay 259bee39c2
tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00
Jacob Lifshay 643816d5b5
vcd: handle enums with fields
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2024-12-04 21:03:29 -08:00
Jacob Lifshay 42afd2da0e
sim: implement enums (except for connecting unequal enum types)
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2024-12-04 20:58:39 -08:00
Jacob Lifshay 15bc304bb6
impl ToExpr for TargetBase 2024-12-04 20:57:44 -08:00
Jacob Lifshay 4422157db8
WIP adding enums to simulator
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2024-12-02 21:06:23 -08:00
Jacob Lifshay d3f52292a1
test doc tests in CI
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2024-12-01 20:21:26 -08:00
Jacob Lifshay fd45465d35
sim: add support for registers
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2024-12-01 20:14:13 -08:00
Jacob Lifshay 5e0548db26
vcd: single bit signals have no spaces in their value changes 2024-12-01 20:12:43 -08:00
Jacob Lifshay 12b3ba57f1
add some ExprCastTo supertraits to ResetType to make generic code easier 2024-12-01 20:10:25 -08:00
Jacob Lifshay 965fe53077
deduce_resets: show more debugging info on assertion failure 2024-12-01 20:09:17 -08:00
Jacob Lifshay 3abba7f9eb
simulating circuits with deduced resets works
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2024-11-27 23:52:07 -08:00
Jacob Lifshay 6446b71afd
deduce_resets works!
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2024-11-27 23:24:11 -08:00
Jacob Lifshay d36cf92d7f
make ToReset generic over the reset type 2024-11-27 23:19:55 -08:00
Jacob Lifshay d744d85c66
working on deduce_resets
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2024-11-27 01:31:18 -08:00
Jacob Lifshay 358cdd10c8
add more expr casts 2024-11-27 01:30:28 -08:00
Jacob Lifshay 9128a84284
Merge remote-tracking branch 'origin/master' into adding-simulator
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2024-11-26 21:28:22 -08:00
Jacob Lifshay 546010739a
working on deduce_resets
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2024-11-26 21:26:56 -08:00
Jacob Lifshay 9b5f1218fd
make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00
Jacob Lifshay 89d84551f8
add ResetType to the list of recognized type bounds 2024-11-26 18:52:03 -08:00
Jacob Lifshay c45624e3c2
Fix SInt::for_value not accounting for sign bit for positive values
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Fixes: #4
 2024-11-26 16:26:29 -08:00
Jacob Lifshay 7851bf545c
working on deduce_resets.rs
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2024-11-26 00:07:11 -08:00
Jacob Lifshay 3e3da53bd2
working on deduce_resets
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2024-11-25 00:01:02 -08:00
Jacob Lifshay fa50930ff8
update petgraph dependency to include UnionFind::new_set() 2024-11-25 00:00:26 -08:00
Jacob Lifshay 9516fe03a1
increase rust version in CI too
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2024-11-24 14:46:25 -08:00
Jacob Lifshay 52ab134673
increase rust version to support omitting match arms with uninhabited types
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2024-11-24 14:41:39 -08:00
Jacob Lifshay 698b8adc23
working on deduce_resets pass
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2024-11-24 14:39:32 -08:00
Jacob Lifshay 59be3bd645
WIP working on implementing deduce_resets pass
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2024-11-24 03:44:31 -08:00
Jacob Lifshay 913baa37e9
WIP adding deduce_resets pass
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2024-11-22 16:07:18 -08:00
Jacob Lifshay 11ddbc43c7
writing VCD for combinatorial circuits works!
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2024-11-20 22:53:54 -08:00
Jacob Lifshay c4b5d00419
WIP adding VCD output 2024-11-20 22:53:54 -08:00
Jacob Lifshay 09aa9fbc78
wire up simulator trace writing interface 2024-11-20 22:53:54 -08:00
Jacob Lifshay 288a6b71b9
WIP adding VCD output 2024-11-20 22:53:54 -08:00
Jacob Lifshay 0095570f19
simple combinatorial simulation works! 2024-11-20 22:53:54 -08:00