Commit graph

Select branches

Hide pull requests

master

runtime-generics

square-brackets-generics-experiment

type-deduction

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#2

#20

#21

#22

#23

#24

#25

#26

#27

#3

#5

#7

#8

#9

v0.1.0

v0.2.0

Mono Color

• 62058dc141
  
  fix cargo doc warnings -- convert urls to auto links master Jacob Lifshay 2025-04-01 22:22:54 -0700
• c4b6a0fee6
  
  add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too Jacob Lifshay 2025-04-01 22:05:42 -0700
• 9092e45447
  
  fix #[hdl(sim)] match on enums Jacob Lifshay 2025-03-30 01:25:07 -0700
• a40eaaa2da
  
  expand SimValue support Jacob Lifshay 2025-03-30 00:55:38 -0700
• 5028401a5a
  
  change SimValue to contain and deref to a value and not just contain bits Jacob Lifshay 2025-03-27 23:44:36 -0700
• e0f978fbb6
  
  silence unused m variable warning in #[hdl_module] with an empty body. Jacob Lifshay 2025-03-27 23:17:28 -0700
• ec3a61513b
  
  simulator read/write types must be passive Jacob Lifshay 2025-03-27 23:03:44 -0700
• fdc73b5f3b
  
  add ripple counter test to test simulating alternating circuits and extern modules Jacob Lifshay 2025-03-25 18:53:46 -0700
• a115585d5a
  
  simulator: allow external module generators to wait for value changes and/or clock edges Jacob Lifshay 2025-03-25 18:26:48 -0700
• ab9ff4f2db
  
  simplify setting an extern module simulation Jacob Lifshay 2025-03-21 17:08:29 -0700
• d1bd176b28
  
  implement simulation of extern modules Jacob Lifshay 2025-03-19 17:11:41 -0700
• 920d8d875f
  
  add some missing #[track_caller] Jacob Lifshay 2025-03-19 17:10:51 -0700
• d453755bb2
  
  add ExprPartialEq/ExprPartialOrd impls for PhantomConst Jacob Lifshay 2025-03-10 19:40:03 -0700
• 450e1004b6
  
  fix using fayalite as a dependency Jacob Lifshay 2025-03-09 23:14:14 -0700
• c0c5b550bc
  
  add PhantomConst Jacob Lifshay 2025-03-09 21:03:47 -0700
• 2fa0ea6192
  
  make FillInDefaultedGenerics work with Sizes and not just Types Jacob Lifshay 2025-03-09 20:59:21 -0700
• bd75fdfefd
  
  add efficient prefix-sums and reductions Jacob Lifshay 2025-03-02 23:04:17 -0800
• 50c86e18dc
  
  add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T> Jacob Lifshay 2025-03-02 16:11:05 -0800
• 60734cc9d1
  
  switch CI to use mirrors Jacob Lifshay 2025-03-02 17:43:29 -0800
• 3458c21f44
  
  add #[hdl(cmp_eq)] to implement HdlPartialEq automatically Jacob Lifshay 2025-02-16 20:48:16 -0800
• 43797db36e
  
  sort custom keywords Jacob Lifshay 2025-02-16 20:46:54 -0800
• cdd84953d0
  
  support unknown trait bounds in type parameters Jacob Lifshay 2025-02-13 18:35:30 -0800
• 86a1bb46be
  
  add #[hdl] let destructuring and, while at it, tuple patterns Jacob Lifshay 2025-02-10 22:49:41 -0800
• 209d5b5fe1
  
  fix broken doc links Jacob Lifshay 2025-02-10 22:49:16 -0800
• d4ea826051
  
  sim: fix "label address not set" bug when the last Assignment is conditional Jacob Lifshay 2025-01-15 19:04:40 -0800
• 404a2ee043
  
  tests/sim: add test_array_rw Jacob Lifshay 2025-01-12 21:36:54 -0800
• e3a2ccd41c
  
  properly handle duplicate names in vcd Jacob Lifshay 2025-01-09 22:52:22 -0800
• 3771cea78e
  
  Gather the FIFO debug ports in a bundle Cesar Strauss 2024-12-29 13:17:24 -0300
• dcf865caec
  
  Add assertions and debug ports in order for the FIFO to pass induction Cesar Strauss 2024-12-29 13:12:58 -0300
• 31d01046a8
  
  Initial queue formal proof based on one-entry FIFO equivalence Cesar Strauss 2024-12-29 13:04:01 -0300
• c16726cee6
  
  fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s Jacob Lifshay 2024-12-29 00:48:15 -0800
• b63676d0ca
  
  add test for cfgs Jacob Lifshay 2024-12-27 04:01:53 -0800
• 7005fa3330
  
  implement handling #[cfg] and #[cfg_attr] in proc macro inputs Jacob Lifshay 2024-12-27 04:02:39 -0800
• 2ab8428062
  
  upgrade syn version Jacob Lifshay 2024-12-28 23:34:46 -0800
• 9b06019bf5
  
  make sim::Compiler not print things to stdout unless you ask for it Jacob Lifshay 2024-12-18 21:15:09 -0800
• 36bad52978
  
  sim: fix sim.write to struct Jacob Lifshay 2024-12-18 20:50:50 -0800
• 21c73051ec
  
  sim: add SimValue and reading/writing more than just a scalar Jacob Lifshay 2024-12-18 01:39:35 -0800
• 304d8da0e8
  
  Merge remote-tracking branch 'origin/master' into adding-simulator Jacob Lifshay 2024-12-13 15:06:45 -0800
• 2af38de900
  
  add more memory tests Jacob Lifshay 2024-12-13 15:04:48 -0800
• c756aeec70
  
  tests/sim: add test for memory rw port Jacob Lifshay 2024-12-12 20:50:41 -0800
• 903ca1bf30
  
  sim: simple memory test works! Jacob Lifshay 2024-12-12 19:47:57 -0800
• 8d030ac65d
  
  sim/interpreter: add addresses to instruction listing Jacob Lifshay 2024-12-12 16:25:38 -0800
• 562c479b62
  
  sim/interpreter: fix StatePartLayout name in debug output Jacob Lifshay 2024-12-12 15:06:17 -0800
• 393f78a14d
  
  sim: add WIP memory test Jacob Lifshay 2024-12-11 23:28:15 -0800
• 8616ee4737
  
  tests/sim: test_enums works! Jacob Lifshay 2024-12-11 00:01:04 -0800
• 5087f16099
  
  sim: fix assignments graph by properly including conditions as assignment inputs Jacob Lifshay 2024-12-11 00:00:21 -0800
• 6b31e6d515
  
  sim: add .dot output for Assignments graph for debugging Jacob Lifshay 2024-12-10 23:40:33 -0800
• 564ccb30bc
  
  sim/vcd: fix variable identifiers to follow verilog rules Jacob Lifshay 2024-12-10 23:39:17 -0800
• ca759168ff
  
  tests/sim: add WIP test for enums Jacob Lifshay 2024-12-10 23:37:26 -0800
• e4cf66adf8
  
  sim: implement memories, still needs testing Jacob Lifshay 2024-12-09 23:03:01 -0800
• cd0dd7b7ee
  
  change memory write latency to NonZeroUsize to match read latency being usize Jacob Lifshay 2024-12-09 23:01:40 -0800
• 2e7d685dc7 add module exercising formal verification of memories Cesar Strauss 2024-12-08 15:25:21 -0300
• 9654167ca3
  
  sim: WIP working on memory Jacob Lifshay 2024-12-06 15:53:34 -0800
• 3ed7827485
  
  sim: WIP adding memory support Jacob Lifshay 2024-12-05 21:35:23 -0800
• e504cfebfe
  
  add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference Jacob Lifshay 2024-12-05 20:27:50 -0800
• 9f42cab471
  
  change to version 0.3.0 for breaking change Jacob Lifshay 2024-12-05 20:26:28 -0800
• 259bee39c2
  
  tests/sim: split expected output text into separate files Jacob Lifshay 2024-12-05 18:15:38 -0800
• 643816d5b5
  
  vcd: handle enums with fields Jacob Lifshay 2024-12-04 21:03:29 -0800
• 42afd2da0e
  
  sim: implement enums (except for connecting unequal enum types) Jacob Lifshay 2024-12-04 20:58:39 -0800
• 15bc304bb6
  
  impl ToExpr for TargetBase Jacob Lifshay 2024-12-04 20:57:44 -0800
• 4422157db8
  
  WIP adding enums to simulator Jacob Lifshay 2024-12-02 21:06:23 -0800
• d3f52292a1
  
  test doc tests in CI Jacob Lifshay 2024-12-01 20:21:26 -0800
• fd45465d35
  
  sim: add support for registers Jacob Lifshay 2024-12-01 20:14:13 -0800
• 5e0548db26
  
  vcd: single bit signals have no spaces in their value changes Jacob Lifshay 2024-12-01 20:12:43 -0800
• 12b3ba57f1
  
  add some ExprCastTo supertraits to ResetType to make generic code easier Jacob Lifshay 2024-12-01 20:10:25 -0800
• 965fe53077
  
  deduce_resets: show more debugging info on assertion failure Jacob Lifshay 2024-12-01 20:08:43 -0800
• 3abba7f9eb
  
  simulating circuits with deduced resets works Jacob Lifshay 2024-11-27 23:52:07 -0800
• 6446b71afd
  
  deduce_resets works! Jacob Lifshay 2024-11-27 23:20:22 -0800
• d36cf92d7f
  
  make ToReset generic over the reset type Jacob Lifshay 2024-11-27 23:19:55 -0800
• d744d85c66
  
  working on deduce_resets Jacob Lifshay 2024-11-27 01:31:18 -0800
• 358cdd10c8
  
  add more expr casts Jacob Lifshay 2024-11-27 01:30:28 -0800
• 9128a84284
  
  Merge remote-tracking branch 'origin/master' into adding-simulator Jacob Lifshay 2024-11-26 21:28:22 -0800
• 546010739a
  
  working on deduce_resets Jacob Lifshay 2024-11-26 21:26:56 -0800
• 9b5f1218fd
  
  make ClockDomain and Reg generic over reset type Jacob Lifshay 2024-11-26 20:47:03 -0800
• 89d84551f8
  
  add ResetType to the list of recognized type bounds Jacob Lifshay 2024-11-26 18:52:03 -0800
• c45624e3c2
  
  Fix SInt::for_value not accounting for sign bit for positive values Jacob Lifshay 2024-11-26 16:26:29 -0800
• 7851bf545c
  
  working on deduce_resets.rs Jacob Lifshay 2024-11-26 00:07:11 -0800
• 3e3da53bd2
  
  working on deduce_resets Jacob Lifshay 2024-11-25 00:01:02 -0800
• fa50930ff8
  
  update petgraph dependency to include UnionFind::new_set() Jacob Lifshay 2024-11-25 00:00:26 -0800
• 9516fe03a1
  
  increase rust version in CI too Jacob Lifshay 2024-11-24 14:46:25 -0800
• 52ab134673
  
  increase rust version to support omitting match arms with uninhabited types Jacob Lifshay 2024-11-24 14:41:39 -0800
• 698b8adc23
  
  working on deduce_resets pass Jacob Lifshay 2024-11-24 14:39:32 -0800
• 59be3bd645
  
  WIP working on implementing deduce_resets pass Jacob Lifshay 2024-11-24 03:44:31 -0800
• 913baa37e9
  
  WIP adding deduce_resets pass Jacob Lifshay 2024-11-22 16:07:18 -0800
• 11ddbc43c7
  
  writing VCD for combinatorial circuits works! Jacob Lifshay 2024-11-20 22:36:12 -0800
• c4b5d00419
  
  WIP adding VCD output Jacob Lifshay 2024-11-18 03:04:10 -0800
• 09aa9fbc78
  
  wire up simulator trace writing interface Jacob Lifshay 2024-11-17 21:02:44 -0800
• 288a6b71b9
  
  WIP adding VCD output Jacob Lifshay 2024-11-17 01:02:00 -0800
• 0095570f19
  
  simple combinatorial simulation works! Jacob Lifshay 2024-11-14 20:28:43 -0800
• f54e55a143
  
  Simulation::settle_step() works for simple modules Jacob Lifshay 2024-11-13 21:20:15 -0800
• a6e40839ac
  
  simulator WIP: use petgraph for topological sort over assignments Jacob Lifshay 2024-11-13 04:14:04 -0800
• 3106a6fff6
  
  working on simulator... Jacob Lifshay 2024-11-12 22:11:12 -0800
• f338f37d3e
  
  working on simulator Jacob Lifshay 2024-11-12 01:08:32 -0800
• 277d3e0d4d
  
  working on simulator Jacob Lifshay 2024-11-10 22:12:57 -0800
• b288d6f8f2
  
  add missing copyright headers Jacob Lifshay 2024-11-07 21:50:31 -0800
• 479d59b287
  
  WIP implementing simulator Jacob Lifshay 2024-11-07 21:46:34 -0800
• 6f904148c4
  
  WIP adding simulator Jacob Lifshay 2024-11-07 01:19:07 -0800
• 3ea0d98924
  
  always write formal cache json Jacob Lifshay 2024-11-20 22:51:40 -0800
• c1f1a8b749 Add test module exercising formal verification. Cesar Strauss 2024-11-20 17:39:00 -0300
• 3d5d8c54b6
  
  add repository to cache key Jacob Lifshay 2024-10-30 20:55:02 -0700