Incorrect number of bits for signed range #4

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opened 2024-11-26 22:44:21 +00:00 by cesar · 1 comment

cesar commented

2024-11-26 22:44:21 +00:00

Owner

Please consider:

    #[test]
    fn test_signed_range() {
        let ty = fayalite::int::SInt::range_inclusive(-1..=7);
        // Need space for sign bit
        assert_eq!(ty.width, 4);
    }

It currently gives:

assertion `left == right` failed
  left: 3
 right: 4

As I understand it, we need an extra sign bit, otherwise -1 and 7 have the same representation.

Please consider: ```rust #[test] fn test_signed_range() { let ty = fayalite::int::SInt::range_inclusive(-1..=7); // Need space for sign bit assert_eq!(ty.width, 4); } ``` It currently gives: ``` assertion `left == right` failed left: 3 right: 4 ``` As I understand it, we need an extra sign bit, otherwise -1 and 7 have the same representation.

programmerjake commented

2024-11-27 00:17:59 +00:00

Owner

thanks! the bug is here, i'll fix it shortly:

Sign::Plus => v.bits(),

thanks! the bug is here, i'll fix it shortly: https://git.libre-chip.org/libre-chip/fayalite/src/commit/3ea0d9892412cbdae1dc8b886d9339e51c532c52/crates/fayalite/src/int.rs#L456