909 commits

Author	SHA1	Message	Date
Clifford Wolf	e218f0eacf	Added support for non-standard <plugin>:<c_name> DPI syntax	2014-08-22 14:30:29 +02:00
Clifford Wolf	74af3a2b70	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	2014-08-22 14:22:09 +02:00
Clifford Wolf	ad146c2582	Fixed small memory leak in ast simplify	2014-08-21 17:33:40 +02:00
Clifford Wolf	6c5cafcd8b	Added support for DPI function with different names in C and Verilog	2014-08-21 17:22:04 +02:00
Clifford Wolf	085c8e873d	Added AstNode::asInt()	2014-08-21 17:11:51 +02:00
Clifford Wolf	490d7a5bf2	Fixed memory leak in DPI function calls	2014-08-21 13:09:47 +02:00
Clifford Wolf	7bfc4ae120	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
Clifford Wolf	38addd4c67	Added support for global tasks and functions	2014-08-21 12:42:28 +02:00
Clifford Wolf	640d9fc551	Added "via_celltype" attribute on task/func	2014-08-18 14:29:30 +02:00
Clifford Wolf	acb435b6cf	Added const folding of AST_CASE to AST simplifier	2014-08-18 00:02:30 +02:00
Clifford Wolf	64713647a9	Improved AST ProcessGenerator performance	2014-08-17 02:17:49 +02:00
Clifford Wolf	d491fd8c19	Use stackmap<> in AST ProcessGenerator	2014-08-17 00:57:24 +02:00
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	83e2698e10	AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map	2014-08-16 19:31:59 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	c7afbd9d8e	Fixed bug in "read_verilog -ignore_redef"	2014-08-15 01:53:22 +02:00
Clifford Wolf	978a933b6a	Added RTLIL::SigSpec::to_sigbit_map()	2014-08-14 23:14:47 +02:00
Clifford Wolf	c83b990458	Changed the AST genWidthRTLIL subst interface to use a std::map	2014-08-14 23:02:07 +02:00
Clifford Wolf	6d56172c0d	Fixed line numbers when using here-doc macros	2014-08-14 22:26:30 +02:00
Clifford Wolf	85e3cc12ac	Fixed handling of task outputs	2014-08-14 22:26:10 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	f53984795d	Added support for non-standard """ macro bodies	2014-08-13 13:03:38 +02:00
Clifford Wolf	593264e9ed	Fixed building verific bindings	2014-08-12 15:21:06 +02:00
Clifford Wolf	2dc3333734	Also allow "module foobar(input foo, output bar, ...);" syntax	2014-08-07 16:41:27 +02:00
Clifford Wolf	d259abbda2	Added AST_MULTIRANGE (arrays with more than 1 dimension)	2014-08-06 15:52:54 +02:00
Clifford Wolf	91dd87e60b	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
Clifford Wolf	0129d41efa	Fixed AST handling of variables declared inside a functions main block	2014-08-05 08:35:51 +02:00
Clifford Wolf	b5a3419ac2	Added support for non-standard "module mod_name(...);" syntax	2014-08-04 15:40:07 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	bd74ed7da4	Replaced sha1 implementation	2014-08-01 19:01:10 +02:00
Clifford Wolf	c6fd82c70b	Fixed build of verific bindings	2014-07-31 16:45:23 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7daad40ca4	Fixed counting verilog line numbers for "// synopsys translate_off" sections	2014-07-30 20:18:48 +02:00
Clifford Wolf	e605af8a49	Fixed Verilog pre-processor for files with no trailing newline	2014-07-29 20:14:25 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	48822e79a3	Removed left over debug code	2014-07-28 19:38:30 +02:00
Clifford Wolf	ec58965967	Fixed part selects of parameters	2014-07-28 19:24:28 +02:00
Clifford Wolf	a03297a7df	Set results of out-of-bounds static bit/part select to undef	2014-07-28 16:09:50 +02:00
Clifford Wolf	55521c085a	Fixed RTLIL code generator for part select of parameter	2014-07-28 15:31:19 +02:00
Clifford Wolf	0598bc8708	Fixed width detection for part selects	2014-07-28 15:19:34 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	3c45277ee0	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	ee65dea738	Fixed signdness detection of expressions with bit- and part-selects	2014-07-28 10:10:08 +02:00
Clifford Wolf	c4bdba78cb	Added proper Design->addModule interface	2014-07-27 21:12:09 +02:00
Clifford Wolf	7661ded8dd	Fixed verific bindings for new RTLIL api	2014-07-27 12:00:28 +02:00