Using log_assert() instead of assert()

frontends/ast/ast.cc

@@ -820,7 +820,7 @@ RTLIL::Const AstNode::realAsConst(int width)
 // create a new AstModule from an AST_MODULE AST node
 static AstModule* process_module(AstNode *ast, bool defer)
 {
-	assert(ast->type == AST_MODULE);
+	log_assert(ast->type == AST_MODULE);
 
 	if (defer)
 		log("Storing AST representation for module `%s'.\n", ast->str.c_str());
@@ -925,7 +925,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	flag_icells = icells;
 	flag_autowire = autowire;
 
-	assert(current_ast->type == AST_DESIGN);
+	log_assert(current_ast->type == AST_DESIGN);
 	for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
 		if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
 			(*it)->str = (*it)->str.substr(1);

frontends/ast/genrtlil.cc

@@ -32,7 +32,6 @@
 
 #include <sstream>
 #include <stdarg.h>
-#include <assert.h>
 #include <algorithm>
 
 using namespace AST;
@@ -137,7 +136,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 // helper function for creating RTLIL code for multiplexers
 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
-	assert(cond.size() == 1);
+	log_assert(cond.size() == 1);
 
 	std::stringstream sstr;
 	sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
@@ -267,7 +266,7 @@ struct AST_INTERNAL::ProcessGenerator
 			sync->type = RTLIL::SyncType::STi;
 			proc->syncs.push_back(sync);
 
-			assert(init_lvalue.size() == init_rvalue.size());
+			log_assert(init_lvalue.size() == init_rvalue.size());
 
 			int offset = 0;
 			for (auto &init_lvalue_c : init_lvalue.chunks()) {
@@ -316,7 +315,7 @@ struct AST_INTERNAL::ProcessGenerator
 		case AST_CASE:
 			for (auto child : ast->children)
 				if (child != ast->children[0]) {
-					assert(child->type == AST_COND);
+					log_assert(child->type == AST_COND);
 					collect_lvalues(reg, child, type_eq, type_le, false);
 				}
 			break;
@@ -341,7 +340,7 @@ struct AST_INTERNAL::ProcessGenerator
 			break;
 
 		default:
-			assert(0);
+			log_abort();
 		}
 
 		if (run_sort_and_unify)
@@ -371,7 +370,7 @@ struct AST_INTERNAL::ProcessGenerator
 			init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
 			lvalue.remove2(initSyncSignals, &rvalue);
 		}
-		assert(lvalue.size() == rvalue.size());
+		log_assert(lvalue.size() == rvalue.size());
 
 		int offset = 0;
 		for (auto &lvalue_c : lvalue.chunks()) {
@@ -445,7 +444,7 @@ struct AST_INTERNAL::ProcessGenerator
 				{
 					if (child == ast->children[0])
 						continue;
-					assert(child->type == AST_COND);
+					log_assert(child->type == AST_COND);
 
 					subst_lvalue_from = backup_subst_lvalue_from;
 					subst_lvalue_to = backup_subst_lvalue_to;
@@ -815,9 +814,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_error("Re-definition of memory `%s' at %s:%d!\n",
 						str.c_str(), filename.c_str(), linenum);
 
-			assert(children.size() >= 2);
-			assert(children[0]->type == AST_RANGE);
-			assert(children[1]->type == AST_RANGE);
+			log_assert(children.size() >= 2);
+			log_assert(children[0]->type == AST_RANGE);
+			log_assert(children[1]->type == AST_RANGE);
 
 			if (!children[0]->range_valid || !children[1]->range_valid)
 				log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
@@ -902,7 +901,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 		use_const_chunk:
 			if (children.size() != 0) {
-				assert(children[0]->type == AST_RANGE);
+				log_assert(children[0]->type == AST_RANGE);
 				if (!children[0]->range_valid) {
 					AstNode *left_at_zero_ast = children[0]->children[0]->clone();
 					AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
@@ -1300,7 +1299,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					}
 					continue;
 				}
-				assert(0);
+				log_abort();
 			}
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)

frontends/ast/simplify.cc

@@ -57,7 +57,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 	if (stage == 0)
 	{
-		assert(type == AST_MODULE);
+		log_assert(type == AST_MODULE);
 
 		while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
 
@@ -73,7 +73,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			{
 				AstNode *mem = it.first;
 				uint32_t memflags = it.second;
-				assert((memflags & ~0x00ffff00) == 0);
+				log_assert((memflags & ~0x00ffff00) == 0);
 
 				if (mem->get_bool_attribute("\\nomem2reg"))
 					continue;
@@ -480,7 +480,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			// dumpAst(NULL, ">   ");
 			log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum);
 		}
-		assert(children[1]->type == AST_IDENTIFIER);
+		log_assert(children[1]->type == AST_IDENTIFIER);
 		newNode = children[1]->clone();
 		const char *second_part = children[1]->str.c_str();
 		if (second_part[0] == '\\')
@@ -506,7 +506,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		range_valid = false;
 		range_left = -1;
 		range_right = 0;
-		assert(children.size() >= 1);
+		log_assert(children.size() >= 1);
 		if (children[0]->type == AST_CONSTANT) {
 			range_valid = true;
 			range_left = children[0]->integer;
@@ -963,8 +963,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 		std::vector<AstNode*> children_list;
 		for (auto child : children) {
-			assert(child->type == AST_ARGUMENT);
-			assert(child->children.size() == 1);
+			log_assert(child->type == AST_ARGUMENT);
+			log_assert(child->children.size() == 1);
 			children_list.push_back(child->children[0]);
 			child->children.clear();
 			delete child;
@@ -1019,7 +1019,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				op_type = AST_POS;
 			if (str == "not")
 				op_type = AST_POS, invert_results = true;
-			assert(op_type != AST_NONE);
+			log_assert(op_type != AST_NONE);
 
 			AstNode *node = children_list[1];
 			if (op_type != AST_POS)
@@ -1423,13 +1423,13 @@ skip_dynamic_range_lvalue_expansion:;
 
 		if (current_block == NULL)
 		{
-			assert(type == AST_FCALL);
+			log_assert(type == AST_FCALL);
 
 			AstNode *wire = NULL;
 			for (auto child : decl->children)
 				if (child->type == AST_WIRE && child->str == str)
 					wire = child->clone();
-			assert(wire != NULL);
+			log_assert(wire != NULL);
 
 			wire->str = prefix + str;
 			wire->port_id = 0;
@@ -1714,7 +1714,7 @@ skip_dynamic_range_lvalue_expansion:;
 				} else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) {
 					RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
 					RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
-					assert(a.bits.size() == b.bits.size());
+					log_assert(a.bits.size() == b.bits.size());
 					for (size_t i = 0; i < a.bits.size(); i++)
 						if (a.bits[i] != b.bits[i])
 							a.bits[i] = RTLIL::State::Sx;
@@ -1761,7 +1761,7 @@ apply_newNode:
 		// fprintf(stderr, "----\n");
 		// dumpAst(stderr, "- ");
 		// newNode->dumpAst(stderr, "+ ");
-		assert(newNode != NULL);
+		log_assert(newNode != NULL);
 		newNode->filename = filename;
 		newNode->linenum = linenum;
 		newNode->cloneInto(this);
@@ -1937,7 +1937,7 @@ void AstNode::mem2reg_as_needed_pass1(std::map<AstNode*, std::set<std::string>>
 
 	uint32_t backup_flags = flags;
 	flags |= children_flags;
-	assert((flags & ~0x000000ff) == 0);
+	log_assert((flags & ~0x000000ff) == 0);
 
 	for (auto child : children)
 		if (ignore_children_counter > 0)
@@ -1986,11 +1986,11 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 		mod->children.push_back(wire_data);
 		while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
 
-		assert(block != NULL);
+		log_assert(block != NULL);
 		size_t assign_idx = 0;
 		while (assign_idx < block->children.size() && block->children[assign_idx] != this)
 			assign_idx++;
-		assert(assign_idx < block->children.size());
+		log_assert(assign_idx < block->children.size());
 
 		AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
 		assign_addr->children[0]->str = id_addr;
@@ -2091,7 +2091,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 				size_t assign_idx = 0;
 				while (assign_idx < block->children.size() && !block->children[assign_idx]->contains(this))
 					assign_idx++;
-				assert(assign_idx < block->children.size());
+				log_assert(assign_idx < block->children.size());
 				block->children.insert(block->children.begin()+assign_idx, case_node);
 				block->children.insert(block->children.begin()+assign_idx, assign_addr);
 			}
@@ -2113,7 +2113,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 			children.push_back(bit_part_sel);
 	}
 
-	assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);
+	log_assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);
 
 	auto children_list = children;
 	for (size_t i = 0; i < children_list.size(); i++)
@@ -2123,7 +2123,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 // calulate memory dimensions
 void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
 {
-	assert(type == AST_MEMORY);
+	log_assert(type == AST_MEMORY);
 
 	mem_width = children[0]->range_left - children[0]->range_right + 1;
 	mem_size = children[1]->range_left - children[1]->range_right;

frontends/verific/verific.cc

@@ -22,7 +22,6 @@
 #include "kernel/log.h"
 #include <unistd.h>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 #include <dirent.h>

frontends/verilog/const2ast.cc

@@ -36,7 +36,6 @@
 
 #include "verilog_frontend.h"
 #include "kernel/log.h"
-#include <assert.h>
 #include <string.h>
 #include <math.h>
 
@@ -47,7 +46,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
 {
 	int carry = 0;
 	for (size_t i = 0; i < digits.size(); i++) {
-		assert(digits[i] < 10);
+		log_assert(digits[i] < 10);
 		digits[i] += carry * 10;
 		carry = digits[i] % 2;
 		digits[i] /= 2;

frontends/verilog/preproc.cc

@@ -37,7 +37,6 @@
 #include <stdarg.h>
 #include <stdio.h>
 #include <string.h>
-#include <assert.h>
 
 static std::list<std::string> output_code;
 static std::list<std::string> input_buffer;
@@ -65,7 +64,7 @@ static char next_char()
 	if (input_buffer.empty())
 		return 0;
 
-	assert(input_buffer_charp <= input_buffer.front().size());
+	log_assert(input_buffer_charp <= input_buffer.front().size());
 	if (input_buffer_charp == input_buffer.front().size()) {
 		input_buffer_charp = 0;
 		input_buffer.pop_front();

frontends/verilog/verilog_frontend.cc

@@ -33,7 +33,6 @@
 #include "libs/sha1/sha1.h"
 #include <sstream>
 #include <stdarg.h>
-#include <assert.h>
 
 using namespace VERILOG_FRONTEND;
 

frontends/vhdl2verilog/vhdl2verilog.cc

@@ -22,7 +22,6 @@
 #include "kernel/log.h"
 #include <unistd.h>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 #include <dirent.h>