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Added $shift and $shiftx cell types (needed for correct part select behavior)

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This commit is contained in:
Clifford Wolf 2014-07-29 14:42:33 +02:00
parent 48822e79a3
commit 397b00252d
12 changed files with 214 additions and 40 deletions
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16
frontends/ast/genrtlil.cc
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@ -917,11 +917,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
children[0]->children[1]->clone() : children[0]->children[0]->clone());
fake_ast->children[0]->delete_children();
RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
if (id2ast->range_right != 0)
shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right);
if (id2ast->range_swapped)
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val);
RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width, fake_ast->children[0]->genRTLIL(), shift_val);
if (id2ast->range_right != 0) {
shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
fake_ast->children[1]->is_signed = true;
}
if (id2ast->range_swapped) {
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
fake_ast->children[1]->is_signed = true;
}
if (SIZE(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
delete left_at_zero_ast;
delete right_at_zero_ast;
delete fake_ast;