3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 01:55:33 +00:00

Added proper Design->addModule interface

This commit is contained in:
Clifford Wolf 2014-07-27 21:12:09 +02:00
parent 5da343b7de
commit c4bdba78cb
3 changed files with 43 additions and 4 deletions

View file

@ -1051,6 +1051,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
RTLIL::Module *AstModule::clone() const
{
AstModule *new_mod = new AstModule;
new_mod->name = name;
cloneInto(new_mod);
new_mod->ast = ast->clone();